This position involves developing timing constraints and performing timing-closure signoff for low-power wireless SoCs and IP systems. The devices are multi-core, multi-threaded processor subsystems with multi-level cache, support multiple wireless protocols and application functionality such as sensor hubs and AI/ML, and are designed to exceed best-in-class power targets. They use complex, deeply gated clock networks with many asynchronous clock sources.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
Job Type
Full-time
Career Level
Senior