Physical Design Lead, Static Timing Analysis

Google•Sunnyvale, CA

6d•$192,000 - $278,000

About The Position

Drive Static Timing Analysis (STA) in the physical implementation of application-specific integrated circuits (ASICs) using advanced technology nodes. Lead timing margin derivation, constraint development and validation, and timing closure for large, complex, high-performance compute ASICs. Develop static timing methodologies, margins, automation scripts, and documentation, and work with architecture, logic design, and Design for Testing (DFT) teams to implement cross-functional design requirements. The role focuses on Google's TPU technology and AI/ML hardware acceleration. It is part of the AI and Infrastructure team, which delivers AI and infrastructure capabilities at scale for Google customers, Googlers, and users worldwide.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in static timing analysis (STA), including 5 years in a technical leadership capacity.
Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints such as Synopsys Design Constraints (SDC).
Experience using Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, or crosstalk.
Experience using EDA tools such as PrimeTime, Tempus, Timevision, or STAR-RC.
Experience analyzing cross-chip clock distribution networks.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
12 years of experience in static timing analysis and 5 years of experience leading STA activities for SoC.
Experience leading physical design or STA flows and methodologies through successful tape-outs and silicon shipments.
Experience analyzing data trends, semiconductor device physics, SPICE simulation, and full-chip static timing topics.
Exceptional track record of on-time STA sign-off and delivery within physical design execution cycles.
Experience driving full-chip timing convergence, timing constraint validation, and complex timing ECO implementation and sign-off.

Responsibilities

Lead timing constraint creation and validation, timing analysis, timing Engineering Change Order (ECO) creation, and final timing sign-off for complex ASICs.
Drive static timing analysis methodology development and support, as well as chip implementation and timing sign-off execution.
Develop, support, and execute implementation flows using industry-standard static timing and parasitic extraction tools.
Interface with the broader team to triage and resolve reported technical issues, escalating complex tool-related problems to EDA vendors and delivering timely solutions.
Lead collaboration with RTL design and DFT teams for high-quality integrations and timing constraints.
Lead timing margin derivation, constraint development and validation, and timing closure for large, complex, high-performance compute ASICs.
Develop static timing methodologies, margins, automation scripts, and documentation.
Work with architecture, logic design, and DFT teams to implement cross-functional design requirements.