Staff Verification Engineer

Renesas Electronics•Plano, TX

7d•Onsite

About The Position

Renesas is seeking an experienced Staff Verification Engineer to verify and model mixed-signal automotive power management devices, including PMICs, switching regulators, and related analog IP. The engineer will work closely with design, systems, validation, and CAD teams to support the development, integration, and sign-off of complex mixed-signal power chips. The role includes architecting verification environments and integrating Real Number Models (RNM) and Analog Mixed Signal (AMS) models; developing verification plans for automotive PMICs; debugging analog and digital design issues; setting up and optimizing Gate-Level Simulation (GLS) flows; and running RTL and gate-level simulations across process, voltage, and temperature corners. The engineer will also collaborate with design, application engineering, ATE, and silicon validation teams, improve verification tools and methodologies, and maintain verification documentation and coverage metrics. Renesas is an embedded semiconductor solution provider with a global team of more than 21,000 engineers and problem solvers in over 30 countries. Its TAGIE culture is grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas offers a competitive benefits package alongside salary; further information is provided during the hiring process. The role is not available for remote work. The position may involve technology subject to U.S. export controls, which may require a government export license before technology is released to certain persons.

Requirements

MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
At least 8 years of experience in mixed-signal or analog circuit verification.
Deep understanding of mixed-signal verification environment architecture and implementation.
Hands-on experience with RNM and AMS model integration.
Proficiency with RTL and behavioral simulation tools, such as Spectre and Xcelium.
Strong understanding of GLS flows and ability to set up and debug GLS simulations.
Expertise debugging analog blocks, including switched-mode regulators, LDOs, bandgaps, and reference circuits, as well as digital RTL.
Experience with automotive PMIC or power management IC design and verification.
Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
Understanding of verification methodologies, including UVM, assertions, and coverage-driven verification.
Experience interfacing with functional, post-silicon, and ATE test-correlation verification domains.
Excellent problem-solving and debugging skills with a strong analytical mindset.
Leadership and mentoring experience.

Responsibilities

Design and architect mixed-signal verification environments, including RNM and AMS model integration for PMIC designs.
Develop and implement verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards including ISO 26262 and AEC-Q200.
Lead debugging activities for analog blocks, including switched-mode regulators, LDO regulators, and mixed-signal interfaces.
Set up and optimize GLS flows, correlating results with RTL simulations to identify and resolve discrepancies.
Conduct RTL and gate-level simulations and analyze timing, power, and functional correctness across PVT corners.
Collaborate with Design, Application Engineering, ATE, and Silicon Validation teams to support verification handoffs.
Troubleshoot design issues involving interactions between analog and digital domains using simulation and measurement techniques.
Improve verification tools, methodologies, and infrastructure, including evaluating emerging verification technologies and AI-based solutions.
Create and maintain verification documentation, test plans, and coverage metrics.