Staff Mixed Signal Verification Engineer

Renesas Electronics•Chandler, AZ

About The Position

As a Mixed-Signal Verification Engineer, you will verify and model mixed-signal power management devices, including PMICs, battery chargers, switching regulators, and related analog IP. You will work with design, systems, verification, CAD, and customer teams to support development, integration, and sign-off of complex mixed-signal power chips. The role leads chip-level verification of analog and mixed-signal circuits using AMS and DMS methodologies, integrating analog behavioral models with digital RTL and UVM-based environments. It develops verification strategies, drives coverage closure, and supports product tapeout milestones. You will create, maintain, and validate SystemVerilog RNM and Verilog-AMS behavioral models, ensuring model accuracy against specifications and schematic references across operating conditions. You will develop and execute traceable verification and modeling plans, monitor readiness, identify schedule risks, and own debugging and root-cause analysis of verification issues. The role partners with engineering teams to improve modeling accuracy, simulation efficiency, and verification quality; contributes verification and modeling perspectives to architecture and design reviews; and supports silicon validation by correlating simulation predictions with bench measurements. You will document plans, model validation methodologies, coverage results, and sign-off metrics, and interface with external customers to present status, discuss coverage, address technical questions, and ensure deliverables meet requirements.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
8–12+ years of experience in mixed-signal verification, AMS/DMS simulation, behavioral modeling, power management IC development, or related semiconductor design activities.
Strong communication, teamwork, and customer-facing skills.
Ability to collaborate across cross-functional engineering teams and present technical information to internal and external stakeholders.

Nice To Haves

Strong experience with switching regulators, battery chargers, PMICs, SystemVerilog, Verilog-AMS, UVM, Cadence Xcelium, Spectre, and mixed-signal verification sign-off methodologies.
Experience developing behavioral models and debugging complex analog-digital interactions.

Responsibilities

Lead chip-level verification of analog and mixed-signal circuits using AMS and DMS methodologies, integrating behavioral models with digital RTL and UVM-based environments.
Develop verification strategies, drive coverage closure, and support product tapeout milestones.
Create, maintain, and validate behavioral models using SystemVerilog RNM and Verilog-AMS.
Correlate model behavior against specifications and schematic references across operating conditions.
Develop and execute verification and modeling plans with traceability from design requirements through coverage closure and tapeout sign-off.
Track verification readiness and proactively identify risks to product schedules.
Own debugging and root-cause analysis of test failures, model inaccuracies, analog-digital interface problems, convergence issues, and simulation performance bottlenecks.
Collaborate with design, modeling, verification, systems, and CAD teams to improve modeling accuracy, simulation efficiency, and verification quality.
Participate in architecture and design reviews, recommending design choices that improve verification effectiveness and reduce risk.
Support silicon validation and root-cause analysis by correlating simulation predictions with bench measurements.
Document verification plans, model validation methodologies, coverage results, and sign-off metrics.
Present verification status and coverage results to external customers, address technical questions, and ensure deliverables meet requirements.