Staff Design Verification Engineer

Renesas Electronics•Plano, AZ

About The Position

Renesas is seeking an experienced Staff Verification Engineer to verify and model mixed-signal automotive power-management devices, including PMICs, switching regulators, and related analog IP. The role works closely with design, systems, validation, and CAD teams to support development, integration, and sign-off of complex mixed-signal power chips. The engineer will architect mixed-signal verification environments, integrate Real Number Models (RNM) and AMS models, develop verification strategies for automotive PMIC products, and lead debugging across analog and digital design domains. The position also involves setting up and optimizing gate-level simulation flows, analyzing RTL and gate-level simulations across PVT corners, collaborating with cross-functional teams, improving verification methods and infrastructure, and maintaining verification documentation and coverage metrics.

Requirements

MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
At least 8 years of experience in mixed-signal or analog circuit verification.
Deep understanding of mixed-signal verification environment architecture and implementation.
Hands-on experience with RNM and AMS model integration.
Proficiency with RTL and behavioral simulation tools, such as Spectre and Xcelium.
Strong understanding of GLS flows and ability to set up and debug GLS simulations.
Experience debugging analog blocks, including switched-mode regulators, LDOs, bandgaps, and reference circuits, as well as digital RTL.
Experience with automotive PMIC or power-management IC design and verification.
Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
Understanding of verification methodologies, including UVM, assertions, and coverage-driven verification.
Experience interfacing with functional verification, post-silicon, and ATE test-correlation domains.
Excellent problem-solving and debugging skills and a strong analytical mindset.
Leadership and mentoring experience.

Responsibilities

Design and architect mixed-signal verification environments, including RNM and AMS model integration for PMIC designs.
Develop and implement verification plans and strategies for automotive PMIC products, with attention to automotive safety standards ISO 26262 and AEC-Q200.
Lead debugging activities for analog blocks, including switched-mode regulators, LDO regulators, and mixed-signal interfaces.
Set up and optimize gate-level simulation (GLS) flows and correlate them with RTL simulation results to identify and resolve discrepancies.
Conduct RTL and gate-level simulations and analyze timing, power, and functional correctness across process, voltage, and temperature (PVT) corners.
Collaborate with Design, Application Engineering, ATE, and Silicon Validation teams to ensure seamless verification handoffs.
Troubleshoot design issues involving interactions between analog and digital domains using simulation and measurement techniques.
Improve verification tools, methodologies, and infrastructure, including evaluating emerging verification technologies and AI-based solutions.
Create and maintain verification documentation, test plans, and coverage metrics.