Staff Design Verification Engineer

Renesas Electronics•Chandler, AZ

About The Position

Renesas is seeking an experienced Staff Verification Engineer to verify and model mixed-signal automotive power-management devices, including PMICs, switching regulators, and related analog IP. The role works closely with design, systems, validation, and CAD teams to support development, integration, and sign-off of complex mixed-signal power chips. It includes architecting verification environments, developing verification strategies for automotive products, debugging analog and digital design issues, and improving verification tools and methodologies.

Requirements

MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
At least 8 years of experience in mixed-signal or analog circuit verification.
Deep understanding of mixed-signal verification environment architecture and implementation.
Hands-on experience with RNM and AMS model integration.
Proficiency with RTL and behavioral simulation tools, such as Spectre and Xcelium.
Strong understanding of GLS flows and ability to set up and debug GLS simulations.
Experience debugging analog blocks such as switched-mode regulators, LDOs, bandgaps, and reference circuits, as well as digital RTL.
Experience with automotive PMIC or power-management IC design and verification.
Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
Understanding of UVM, assertions, and coverage-driven verification.
Experience interfacing with functional verification, post-silicon, and ATE test-correlation domains.
Strong problem-solving, debugging, and analytical skills.
Leadership and mentoring experience.

Responsibilities

Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS model integration for PMIC designs.
Develop and implement verification plans and strategies for automotive PMIC products, ensuring compliance with ISO 26262 and AEC-Q200.
Lead debugging activities for analog blocks, including switched-mode regulators, LDO regulators, and mixed-signal interfaces.
Set up and optimize Gate-Level Simulation (GLS) flows, correlate them with RTL simulation results, and resolve discrepancies.
Conduct RTL and gate-level simulations and analyze timing, power, and functional correctness across process, voltage, and temperature corners.
Collaborate with Design, Application Engineering, ATE, and Silicon Validation teams to support verification handoffs.
Troubleshoot design issues involving interactions between analog and digital domains using simulation and measurement techniques.
Improve verification tools, methodologies, and infrastructure, and evaluate emerging verification technologies and AI-based solutions.
Create and maintain verification documentation, test plans, and coverage metrics.