ASICS Design Verification Engineer-Senior to Staff

Qualcomm • San Diego, CA

6d • $121,800 - $182,600

About The Position

Qualcomm Technologies, Inc. is seeking an ASICS Design Verification Engineer for its Engineering Group. The team handles the complete verification lifecycle, from system-level concept through tape out and post-silicon support. The role focuses on comprehensive pre-silicon test planning for digital power IP, testbench development using advanced verification methodologies such as SystemVerilog-UVM, coverage and assertion model development, and formal verification through property checking. The engineer will also learn and deploy power-aware UPF verification flows and methodologies and develop automation to improve verification efficiency.

Requirements

• Bachelor's degree in Science, Engineering, or a related field and 2+ years of ASIC design, verification, validation, integration, or related work experience; or a Master's degree in Science, Engineering, or a related field and 1+ year of such experience; or a PhD in Science, Engineering, or a related field.
• Bachelor's degree in Engineering, Science, or a closely related field.
• 2+ years of experience with ASIC design and verification tools, techniques, and methodology.

Nice To Haves

• Master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field.
• 6+ years of experience with ASIC design and verification tools, techniques, and methodology.
• 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL.
• 6+ years of experience with computer architecture fundamentals, object-oriented programming concepts, and C or C++ programming skills.
• 6+ years of experience developing block-level testbench environments using SystemVerilog.
• 6+ years of experience with verification methodologies such as UVM or OVM and exposure to assertion-based formal verification.
• 6+ years of scripting or automation experience using Perl or Python.
• Experience with AMBA bus protocols such as AXI, AHB, or APB is desirable but not mandatory.
• Knowledge of or experience with assertion-based formal verification is desirable but not mandatory.

Responsibilities

• Develop comprehensive pre-silicon test plans for digital power IP.
• Develop testbenches using advanced verification methodologies such as SystemVerilog-UVM.
• Develop coverage and assertion models and perform formal verification (property checking).
• Learn and deploy power-aware UPF verification flows and methodologies.
• Develop automation to improve verification efficiency.
• Contribute to the verification lifecycle from system-level concept through tape out and post-silicon support.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants, except for employees on sales-incentive plans.
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior