ASICS Design Verification Engineer

Qualcomm • San Diego, CA

7d • $101,400 - $152,200

About The Position

The ASICS Design Verification Engineer works on the complete verification lifecycle, from system-level concept through tape out and post-silicon support. The role focuses on comprehensive pre-silicon test planning for digital power IP, testbench development using advanced verification methodologies such as SystemVerilog-UVM, coverage and assertion-model development, and formal verification through property checking. The engineer will learn and deploy power-aware UPF verification flows and methodologies and develop automation to improve verification efficiency.

Requirements

• Bachelor's degree in Engineering, Science, or a closely related field; the minimum qualification also specifies a bachelor's degree in Science, Engineering, or a related field.
• At least 1 year of experience with ASIC design and verification tools, techniques, and methodology.

Nice To Haves

• Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field.
• At least 2 years of experience with ASIC design and verification tools, techniques, and methodology.
• At least 2 years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL.
• At least 2 years of experience with computer architecture fundamentals, object-oriented programming concepts, and C or C++ programming skills.
• At least 2 years of experience developing block-level testbench environments using SystemVerilog.
• At least 2 years of experience with verification methodologies through coursework or past experience, such as UVM or OVM, and exposure to assertion-based formal verification.
• At least 2 years of experience with scripting or automation using Perl or Python.
• Experience with AMBA bus protocols such as AXI, AHB, or APB is desirable but not mandatory.
• Knowledge or experience with assertion-based formal verification is desirable but not mandatory.

Responsibilities

• Plan comprehensive pre-silicon tests for digital power IP.
• Develop testbenches using verification methodologies such as SystemVerilog-UVM.
• Develop coverage and assertion models.
• Perform formal verification, including property checking.
• Learn and deploy power-aware UPF verification flows and methodologies.
• Develop automation to improve verification efficiency.
• Contribute to the verification lifecycle from system-level concept through tape out and post-silicon support.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants; employees on sales-incentive plans are not eligible for the annual bonus.
• Competitive benefits package designed to support success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level