Senior Design Verification Engineer

Microsoft•Redmond, WA

20h•$119,800 - $261,000

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s Intelligent Cloud mission, delivering infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages Microsoft computer chips, including Azure Cobalt. Within CSME, the Shared and Custom IP & Silicon (SCIPS) team supports the quality, delivery, scale, planning, and sustainability of Microsoft cloud hardware. The Senior Design Verification Engineer supports the team’s mission through block- and subsystem-level verification. The role contributes to pre-silicon verification and post-silicon validation of custom IP, including strategy and test-plan development, execution and debugging, silicon bring-up, collaboration across engineering teams, and adoption of AI-based tools and agents. The position is classified as Silicon Engineering IC4. The stated typical U.S. base pay range is $119,800–$234,700 per year; the range for the San Francisco Bay Area and New York City metropolitan area is $160,200–$261,000 per year. Certain roles may be eligible for benefits and other compensation. Applications are accepted on an ongoing basis until the position is filled, and the posting will be open for at least five days.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master’s degree in one of those fields and at least 4 years of technical engineering experience; or a bachelor’s degree in one of those fields and at least 5 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Provide proof of citizenship, U.S. permanent residency, or other protected status to establish eligibility for access to export-controlled information; citizenship will be verified with a valid passport, with other applicable documents available for lawful permanent residents, refugees, and asylees.

Nice To Haves

B.S. or higher in Computer Engineering, Electrical Engineering, or a similar field.
At least 7 years of experience in design verification, developing test plans and verification environments, creating test content, and debugging multiple IPs, subsystems, and/or SoCs.
At least 3 years of experience in silicon bring-up and post-silicon validation for complex ASICs or SoCs.
Extensive experience with end-to-end block- and subsystem-level verification, including test-plan development, execution, and debugging.
Experience developing and executing UVM-based testbenches.
Strong C/C++ programming skills and experience developing and debugging C-based test infrastructure.
Experience developing test firmware for industry-standard processors, including boot flow, interrupt handling, and memory allocation.
In-depth knowledge of verification principles, testbenches, stimulus generation, coverage-based verification, and coverage closure.
Experience with chip bring-up and silicon validation for complex SoCs.
Solid understanding of chip and/or computer architecture.
Strong communication skills and ability to collaborate with a team.
Energetic and self-motivated approach.
Ability to develop innovative solutions using AI.
Experience in formal verification using Jasper.

Responsibilities

Establish a role as an integral member of pre-silicon verification and post-silicon validation teams developing custom IP components.
Define pre-silicon verification strategies using simulation, emulation, and FPGA testing, as well as post-silicon validation strategies, and develop test plans.
Execute end-to-end verification plans at the block, subsystem, or system level.
Apply UVM-based verification methodology, including coverage closure.
Use basic C and C++ programming understanding to develop C-based testbenches.
Plan silicon validation testing and perform silicon bring-up and validation activities.
Collaborate with verification teams on vertical and horizontal reuse of components.
Work with Architecture, Design, Firmware/Software, Product Engineering, Program Management, and third-party vendor teams to ensure pre- and post-silicon testing is comprehensive.
Provide technical leadership through mentorship and teamwork.
Adopt AI-based tools and agents to improve execution efficiency.