Senior Design Verification Engineer

Microsoft•Redmond, WA

15h

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft's cloud infrastructure and supports its online businesses through server and data center infrastructure, security, operations, and related solutions. The Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages Microsoft's computer chips, including Azure Cobalt. The Shared and Custom IP & Silicon team supports hardware manufacturing by improving planning, quality, delivery, scale, and sustainability. The Senior Design Verification Engineer joins a pre-silicon verification and post-silicon validation team, with a key role in block- and sub-system-level verification for custom IP components. The position develops and executes verification and validation strategies and plans, works across technical and vendor teams, and provides technical leadership through mentorship and collaboration. The engineer is also expected to adopt AI-based tools and agents to improve execution.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Must provide citizenship or qualifying protected-status documentation for export-control eligibility assessment; citizenship will be verified with a valid passport, with alternative documents applicable for lawful permanent residents, refugees, and asylees.
Experience in UVM-based verification methodology and coverage closure.
Basic C and C++ programming understanding for development of C-based testbenches.

Nice To Haves

B.S. or higher in Computer Engineering, Electrical Engineering, or a similar field.
7+ years of experience in design verification, developing test plans and verification environments, creating test content, and debugging for multiple IPs, subsystems, and/or SoCs.
3+ years of experience in silicon bring-up and post-silicon validation for complex ASICs or SoCs.
Extensive experience in block- and subsystem-level end-to-end verification, including test-plan development, execution, and debugging.
Experience developing and executing UVM-based testbenches.
Strong C/C++ programming skills and experience developing and debugging C-based test infrastructure.
Experience developing test firmware for industry-standard processors, including boot flow, interrupt handling, and memory allocation.
In-depth knowledge of verification principles, testbenches, stimulus generation, coverage-based verification, and coverage closure.
Experience in chip bring-up and silicon validation for complex SoCs.
Solid understanding of chip and/or computer architecture.
Strong communication skills and ability to work collaboratively with a team.
Energetic and self-motivated approach.
Ability to develop innovative solutions using AI.
Experience in formal verification using Jasper.

Responsibilities

Establish as an integral member of a pre-silicon verification and post-silicon validation team developing custom IP components.
Define pre-silicon verification strategies using simulation, emulation, and FPGA testing, as well as post-silicon validation strategies; develop test plans.
Execute end-to-end verification plans at block, sub-system, or system level.
Apply UVM-based verification methodology, including coverage closure.
Use basic C and C++ programming skills to develop C-based testbenches.
Plan silicon validation testing and perform silicon bring-up and validation activities.
Collaborate across verification teams on vertical and horizontal reuse of components.
Work with Architecture, Design, Firmware/Software, Product Engineering, Program Management, and third-party vendor teams to ensure comprehensive pre- and post-silicon testing.
Provide technical leadership through mentorship and teamwork.
Adopt AI-based tools and agents for efficient execution.