Verification Engineer

Delos Data•Palo Alto, CA

10h

About The Position

The Verification Engineer is responsible for ensuring the functionality, correctness, and quality of complex digital designs across ASIC and FPGA platforms. The role focuses on building robust verification environments, executing coverage-driven verification plans, and collaborating with RTL design engineers to deliver reliable, high-quality silicon. The engineer is expected to drive verification from planning through closure. The company is a startup developing foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. It is headquartered in Silicon Valley and operates across remote and on-site locations in the U.S. and Canada. The company describes a collaborative culture grounded in unity, shared responsibility, trust, integrity, respect, accountability, and meaningful work.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in digital design verification.
Strong hands-on experience with UVM-based or similar verification methodologies.
Proficiency in SystemVerilog, UVM, and Python.
Experience with industry-standard EDA tools such as Synopsys VCS, Siemens/Mentor Questa, or Cadence Xcelium.
Solid understanding of digital design fundamentals.
Experience verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB.
Experience with high-speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C.
Strong analytical and problem-solving skills.
Clear written and verbal communication skills for cross-functional collaboration.
High attention to detail and ability to deliver reliable, high-quality verification outcomes.
Ability to work independently and manage tasks to completion.

Nice To Haves

Experience with formal verification techniques and tools.
Experience verifying processor subsystems or SoC-level designs.

Responsibilities

Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies.
Create and execute coverage-driven verification plans aligned with design specifications.
Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases.
Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with RTL design engineers.
Implement and track functional and code coverage, driving verification to closure.
Develop reusable verification components and write SystemVerilog Assertions (SVA).
Participate in design and verification reviews, providing input on design testability, correctness, and optimization.
Automate regression testing and enhance verification infrastructure using Python and scripting.
Contribute to continuous improvement of verification processes, tools, and methodologies.