Sr/ Staff Design Engineer/Architect(Datapath), HBM

Micron Technology•Richardson, TX

About The Position

Micron Technology’s HBM Architecture team develops advanced datapath solutions for next-generation High Bandwidth Memory (HBM) products. The team works across design, PHY, ECC, verification, layout, and system groups to develop logic-die and core-die architectures from concept through production. The HBM Datapath Engineer will architect, design, and optimize high-speed datapaths for HBM products, focusing on logic-die and core-die circuitry. The role supports bandwidth, power efficiency, reliability, and scalability across JEDEC and custom HBM solutions, and contributes to designs from concept through silicon bring-up and production. The position also includes leveraging AI to efficiently execute regular work.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of relevant industry experience, or a Master’s degree with 4+ years of relevant industry experience.
  • At least 2 years of experience in high-speed digital datapath design in memory, SerDes, or SoC datapath.
  • At least 2 years of hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.

Nice To Haves

  • Strong understanding of HBM/DRAM architectures, including read/write data flow, timing, and multi-channel operation.
  • Working knowledge of layout and floorplanning considerations for high-speed datapath.
  • Experience with static timing analysis (STA) and timing-closure methodologies.
  • Familiarity with advanced process-node challenges related to signal integrity, skew control, and power optimization.

Responsibilities

  • Architect and design HBM read and write datapaths across core and logic die, including alignment, buffering, timing, and control logic.
  • Develop high-speed, low-latency datapath circuits supporting multi-channel HBM architectures and wide internal buses.
  • Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes.
  • Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping mechanisms.
  • Collaborate with multifunctional teams to translate specifications into robust micro-architectures.
  • Work with PHY, DFT, verification, and layout teams to ensure functionality, testability, and manufacturability.
  • Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies.
  • Contribute to design reviews, documentation, and technical mentoring across HBM programs.
  • Leverage AI to efficiently execute regular work.

Benefits

  • Choice of medical, dental, and vision plans.
  • Programs to protect income in the event of illness or injury.
  • Paid family leave.
  • Paid time off.
  • Paid holidays.
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service