Sr/ Staff Design Engineer/Architect(Datapath), HBM

Micron • Richardson, TX

1d

About The Position

Micron Technology’s HBM Architecture team develops advanced datapath solutions for next-generation High Bandwidth Memory products. The Sr/ Staff Design Engineer/Architect will architect, design, and optimize high-speed datapaths for HBM, focusing on logic-die and core-die datapath circuitry to achieve high bandwidth, power efficiency, reliability, and scalability across JEDEC and custom HBM solutions. The role works closely with design, PHY, ECC, verification, layout, and system teams to deliver datapath designs from concept through silicon bring-up and production.

The engineer will develop read and write datapaths, optimize circuit performance, integrate reliability features, and contribute to schematic- and RTL-level implementations. The position also involves design reviews, documentation, technical mentoring, and leveraging AI to efficiently execute regular work.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 6 or more years of relevant industry experience, or a Master’s degree with 4 or more years of relevant industry experience.
• At least 2 years of experience in high-speed digital datapath design in memory, SerDes, or SoC datapath.
• At least 2 years of hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.

Nice To Haves

• Strong understanding of HBM/DRAM architectures, including read/write data flow, timing, and multi-channel operation.
• Working knowledge of layout and floorplanning considerations for high-speed datapath.
• Experience with static timing analysis (STA) and timing-closure methodologies.
• Familiarity with advanced process-node challenges related to signal integrity, skew control, and power optimization.

Responsibilities

• Architect and design HBM read and write datapaths across core and logic die, including alignment, buffering, timing, and control logic.
• Develop high-speed, low-latency datapath circuits for multi-channel HBM architectures and wide internal buses.
• Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes.
• Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping mechanisms.
• Collaborate with multifunctional teams to translate specifications into robust micro-architectures.
• Collaborate with PHY, DFT, verification, and layout teams to ensure functionality, testability, and manufacturability.
• Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies.
• Contribute to design reviews, documentation, and technical mentoring across HBM programs.
• Leverage AI to efficiently execute regular work.

Benefits

• Choice of medical, dental, and vision plans.
• Income-protection benefit programs for illness or injury.
• Paid family leave.
• Paid time off.
• Paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior