SoC Physical Design Methodology Engineer

Apple • San Jose, CA

1d

About The Position

At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.

Requirements

• BS degree with 0 years of relevant industry experience.

Nice To Haves

• Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodology
• Understands RTL to GDS physical design flow
• Scripting skills to debug flow related issues and make enhancements as appropriate
• Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
• Layout design background and experience a plus

Responsibilities

• Perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.
• Collaborate with the CAD/Technology teams for flow bring up and validation.
• Work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
• Lead schedules and support cross-functional engineering efforts.
• Work on padring, bump, RDL design, and working with the package and floorplan teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level