ML and AI Physical Design Methodology Engineer

NVIDIA•Austin, CA

1d•$136,000 - $264,500

About The Position

NVIDIA is seeking an ML/AI Physical Design Methodology Engineer to join its Networking Silicon engineering team, which develops high-speed communication devices. The role focuses on architecting, integrating, and deploying AI/ML-driven solutions in production physical design flows and developing creative solutions to physical design problems to improve power, performance, and area (PPA). The engineer will also contribute to flow and tool methodologies across multiple projects, including place and route, timing analysis and closure, IR and signal-EM convergence, power and noise analysis, back-end verification, chip floorplanning, power and clock distribution, and chip assembly. Data-based analysis and algorithmic methods will be used to check and improve PPA. The position requires a master's degree in electrical engineering, computer engineering, computer science, or equivalent experience, along with at least five years of experience developing ML/AI-based solutions. Strong Python and Tcl programming skills, familiarity with ML frameworks, experience automating workflows, and exposure to physical design workflows are required. The role is offered at Level 3 or Level 4, with base salary ranges of $136,000–$218,500 and $168,000–$264,500, respectively. Equity and benefits are also offered.

Requirements

Master's degree in electrical engineering, computer engineering, computer science, or equivalent experience.
At least 5 years of experience in ML/AI-based solution development.
Experience and ability to form and automate workflows.
Strong Python and Tcl programming skills.
Familiarity with ML frameworks.
Proven implementation of ML-based solutions.
Exposure to physical design workflows.

Responsibilities

Architect, integrate, and deploy AI/ML-driven solutions into production physical design flows.
Develop creative solutions to state-of-the-art physical design problems to improve PPA.
Formulate and develop ML-based solutions.
Develop flow and tool methodologies for place and route, timing analysis and closure, IR and signal-EM convergence, power and noise analysis, and back-end verification across multiple projects.
Contribute to chip floorplanning, power and clock distribution, and chip assembly.
Use data-based analysis and algorithmic solutions for PPA checking and improvement.