RTL Methodology Silicon Design Engineer

Advanced Micro Devices, Inc•Austin, TX

About The Position

As an RTL Methodology Engineer, you will work on AMD’s next-generation CPU core, building infrastructure, tools, and AI-powered capabilities to improve the efficiency and productivity of the Core RTL team. The flows and tools you own will be used by RTL designers across the project, and you will help introduce modern AI and agentic tools into hardware design. You will work with an experienced engineering team and collaborate with Performance Modeling, Design Verification, Physical Design, and Post-Silicon teams to support AMD’s future CPU roadmap. The role focuses on improving RTL engineering methodology, static analysis, automation, and design tooling, as well as contributing to silicon debug and product support when needed.

Requirements

Strong problem-solving and debugging skills.
Strong proficiency with scripting languages such as Python, Perl, Ruby, Shell, and/or TCL.
The role is not eligible for visa sponsorship.

Nice To Haves

Verilog/SystemVerilog RTL development within CPU, SoC, ASIC, or related digital-design environments.
Experience with RTL linting, static analysis, design methodology, and code-quality tooling.
Experience with HDL parsers, ASTs, or source-code analysis and transformation tools such as Verible, Slang, Verilator, Surelog, or comparable technologies.
Experience building applications or engineering tools using large language models, including RAG, agentic frameworks, tool/function calling, prompt engineering, or related approaches.
Experience applying AI coding assistants or agents within engineering-development workflows.
Experience evaluating AI-tool quality and reliability through benchmarking, regression testing, or productivity measurement.
Experience developing and owning internal engineering tools and automation.
Programming experience with Python, Go, Java, C#, TypeScript, or comparable languages.
Familiarity with digital-design workflows including synthesis, verification, physical design, place and route, and timing closure.
A BS, MS, or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field of study is preferred.

Responsibilities

Execute and refine the methodology and tools needed to accomplish RTL design work.
Develop AI-powered tools and agentic workflows to accelerate RTL design, review, debug, and code quality, including LLM-based assistants, code generation and transformation, and automated analysis of design artifacts.
Own and advance the RTL static analysis ecosystem, including linting flows, rule authoring and waiver management, SystemVerilog/Verilog parsers, ASTs, and custom code-analysis tooling.
Identify high-value opportunities to apply AI across the RTL design flow, prototype solutions, and bring successful prototypes into production use.
Collaborate with hardware and infrastructure engineers to develop engineering infrastructure for RTL development.
Own, refine, and maintain critical tools that support successful, high-quality RTL development.
Work with multidisciplinary teams to improve efficiency in RTL development.
Contribute to silicon debug and product support as needed.