SoC Physical Design Engineer, PnR

Apple • San Jose, CA

4d

About The Position

In this visible role at Apple, the SoC Physical Design Engineer is directly responsible for the physical implementation of design partitions, from netlist to tapeout, for a highly complex SoC using innovative process technology. The engineer works at the center of the design effort, collaborating with architecture, CAD, timing, and logic design teams to help deliver high-quality designs.

The role involves knowledge of chip architecture and back-end design flows, including physical synthesis, floor planning, place and route, power grids, static timing analysis, physical design verification, and electrical verification. The engineer completes partition implementation through GDS2, meets schedule and design goals, and drives signoff closure.

Requirements

• Minimum bachelor's degree.
• Basic understanding of logic gates.

Nice To Haves

• Previous internship, co-op, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
• Strong teamwork skills and the ability to collaborate with multiple functional teams across a variety of fields.
• Experience with Verilog, VHDL, Python, Perl, TCL, and/or SPICE.

Responsibilities

• Work with the logic design team to understand partition architecture and address physical design aspects early in the design cycle.
• Complete netlist-to-GDS2 implementation for assigned partitions while meeting schedule and design goals.
• Perform timing, physical, and electrical verification, and drive signoff closure for the partitions.
• Resolve and improve physical design and flow issues, identify potential solutions, and drive their execution.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level