SoC Physical Design Engineer, PnR

Apple • San Jose, CA

2d

About The Position

The SoC Physical Design Engineer is responsible for the physical implementation of one or more design partitions, from netlist through tapeout, for a complex system-on-chip using advanced process technology. The role collaborates with architecture, CAD, timing, and logic design teams to support physical design and deliver high-quality designs.

The position covers physical design activities including physical synthesis, floor planning, place and route, power-grid design, static timing analysis, physical design verification, and electromigration and IR-drop analysis.

Requirements

• Bachelor of Science degree; 0 or more years of experience.
• Basic understanding of logic gates.
• Previous internship or co-op, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
• Strong teamwork skills and ability to collaborate with multiple functional teams across a variety of fields.
• Experience with one or more of Verilog, VHDL, Python, Perl, TCL, or SPICE.
• Knowledge of basic chip architecture and back-end chip design flow, including physical synthesis, floor planning, place and route, power grid, static timing analysis, physical design verification (DRC/LVS), and EMIR tools such as Redhawk, Totem, or Voltus.

Responsibilities

• Work with the logic design team to understand partition architecture and address physical design considerations early in the design cycle.
• Complete netlist-to-GDS2 implementation for assigned partitions while meeting schedule and design goals.
• Perform timing, physical, and electrical verification, and drive signoff closure for the partitions.
• Resolve and improve physical-design-related design and flow issues, identify potential solutions, and drive their execution.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level