SoC DFT Engineer, Cloud

Google•Sunnyvale, CA

3d•$163,000 - $236,000

About The Position

As a DFT Engineer, you will define, implement, and deploy advanced design-for-test (DFT) methodologies—including Scan, MBIST, JTAG, and iJTAG—for highly digital or mixed-signal chips and IPs. You will define silicon test strategies and DFT/DFD architecture, and create DFT and debug specifications for next-generation SoCs. Working with the Silicon Engineering team, you will diagnose memory and logic failures, improve production quality and yield, and reduce test costs. The role supports development of TPU technology for AI/ML hardware acceleration. You will apply design and verification expertise to complex digital designs, with a focus on TPU architecture and integration into AI/ML-driven systems. The position is part of Google’s AI and Infrastructure team, which develops AI and infrastructure capabilities, computing platforms, TPUs, and other technologies.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
At least 5 years of experience in DFT architecture, implementation, and verification for SoCs.
Experience in silicon bring-up, debug, or validation of DFT features.
Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
10 years of experience in DFT architecture, implementation, and verification for SoCs.
Experience with fault models such as Stuck-at, Transition, Cell-Aware, and Path Delay.
Experience with DFT flows, including architecture, IP integration (such as test controllers, TAP, and MBIST), and interaction with synthesis and verification flows.
Experience with industry-leading DFT EDA tools, such as Synopsys Design Compiler or DFT Max, or Siemens EDA Tessent or TestKompress.
Knowledge of test standards such as IEEE 1149.1 and 1687, and test data formats such as BSDL and STIL.

Responsibilities

Develop and document DFT strategy, architecture, and test sequences, including hierarchical DFT, MBIST, ATPG, and I/JTAG, and associated boot-up and execution sequences.
Complete Test Design Rule Checks (TDRC) and make design changes to fix violations and achieve high test quality.
Develop diagnostic databases, software, and hardware for logic and memory failure debug.
Design and implement system-level test strategy.
Implement core DFT circuitry, including scan-chain insertion and hookup, DFT compression, Logic BIST, TAP controllers, and MBIST logic for IP blocks.
Diagnose memory and logic failures in partnership with the Silicon Engineering team.