Principal SoC DFT Engineer, HBM

Micron Technology•Folsom, CA

2d•$199,000 - $347,000

About The Position

As an HBM SoC DFT Engineer within Micron Technology’s Heterogeneous Integration Group (HIG), you will own the DFT architecture, implementation, and signoff of complex HBM base-die SoC designs. You will work within the SoC execution team and collaborate with RTL design, verification, physical design, product engineering, test, probe, and manufacturing teams to deliver robust, scalable, and manufacturable test solutions from pre-silicon development through tapeout and product bring-up. The role includes defining DFT architecture early in the design cycle; implementing and integrating test logic across block, subsystem, and full-chip levels; and executing DFT flows through signoff and coverage closure. You will contribute to standardized DFT methodologies across HBM SoC programs, support pre- and post-silicon debug, mentor junior engineers as appropriate, and develop Gen-AI-driven tools, workflows, and methodologies leveraging Agentic AI. This is a full-time position. The US base salary range is $199,000–$347,000 per year. Additional compensation may include benefits, bonuses, and equity. The job posting describes medical, dental, and vision plans, income-protection programs, paid family leave, paid time off, and paid holidays.

Requirements

Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or a related field.
10 or more years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.
Strong hands-on experience with SoC DFT architecture and implementation.
Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
Familiarity with full RTL-to-GDS SoC flows, including interactions among DFT, synthesis, STA, and physical design.
Experience working with large, complex SoCs involving multiple IPs and subsystems.
Proficiency with industry-standard DFT and implementation EDA tools from Siemens, Synopsys, and/or Cadence.
Strong RTL debugging and design analysis skills.
Familiarity with scripting languages such as Python, Tcl, or Perl for flow automation.
Excellent problem-solving and analytical skills.
Strong written and verbal communication skills and ability to collaborate across global, cross-functional teams.

Nice To Haves

Familiarity with memory systems (DRAM/HBM) and JEDEC specifications.

Responsibilities

Own SoC-level DFT implementation, including scan, MBIST, LBIST as applicable, boundary scan (JTAG), and test access architectures for HBM base-die designs.
Drive DFT architecture definition early in the design cycle, aligning it with SoC integration, floorplanning, timing, power, and physical design constraints.
Implement and integrate DFT logic at block, subsystem, and full-chip levels in collaboration with RTL and integration teams.
Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and DRC/LVS signoff.
Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up.
Support pre-silicon debugging of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis.
Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs.
Maintain technical expertise and mentor junior engineers as appropriate.
Drive innovation for future HBM generations, focusing on quality, scalability, and manufacturability.
Develop Gen-AI-driven tools, workflows, and methodologies that leverage Agentic AI.