DFT Engineer
Nexiva•Santa Clara, CA
•Onsite
About The Position
The Senior DFT Engineer will contribute to SoC or ASIC design programs, applying design-for-test (DFT) expertise across ATPG, MBIST, IO testing, and clock verification. The role includes generating, analyzing, and debugging ATPG patterns and supporting memory, interface, pin-level, and clock-related test and verification activities. The position is onsite in Santa Clara, California. The posting lists Nvidia/LTTS as the client, five openings, a C2C rate of $50–$60, and says relocation works. Local candidates are preferred, with a face-to-face interview.
Requirements
- At least 4 years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
- Strong understanding of DFT fundamentals, including controllability, observability, and scan-based testing.
- Proven expertise in ATPG pattern generation, analysis, and debug.
- Experience with MBIST, including memory test architectures and diagnostics.
- Knowledge of IO test methodologies for interface and pin-level validation.
- Solid understanding of clock DFT and clock verification concepts.
- Strong grasp of digital design and RTL fundamentals.
- Experience with industry-standard DFT/ATPG EDA tools.
- Ability to work effectively in fast-paced, high-performance semiconductor programs.
Nice To Haves
- Local candidates are preferred.
Responsibilities
- Generate, analyze, and debug ATPG patterns.
- Work with MBIST, including memory test architectures and diagnostics.
- Apply IO test methodologies for interface and pin-level validation.
- Support clock DFT and clock verification.
- Contribute DFT expertise to SoC or ASIC designs.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
