SoC Design Verification Engineer

Inspire Semiconductor•Austin, TX

3d•Hybrid

About The Position

We are looking for a SoC Design Verification Engineer to support the complete verification of our innovative System-on-Chip (SoC). This critical role encompasses our RISC-V core, network, and 3rd-party peripheral IP integrations. You will be responsible for developing comprehensive verification plans, building testbenches, and ensuring the highest level of design quality and functional correctness before tape-out.

Requirements

A Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering (or related field).
3+ years of hands-on experience in ASIC/SoC design verification.
Strong proficiency in SystemVerilog, UVM, and simulation tools (e.g., Xcelium).
Solid understanding of digital design fundamentals, RTL design, and synthesis flow.
Experience with functional coverage, assertions, and scoreboarding.
Strong scripting and programming skills (Python, Perl, TCL, C/C++).
Knowledge of common bus protocols (AXI, AHB, PCIe, DDR4/5, etc.).
Working knowledge of version control and continuous integration tools (e.g., Git, Jenkins, Jira, and Confluence).
Solid debugging skills, analytical thinking, and attention to detail.

Nice To Haves

Experience with Formal verification (Conformal LEC).
Hands-on experience with emulation systems (Zebu, Palladium) or FPGA prototypes.
Experience with Cadence EDA tools.

Responsibilities

Develop and execute verification plans for complex SoC digital designs.
Create and maintain UVM/SystemVerilog based testbenches and environments.
Write, debug, and execute constrained-random and directed test cases.
Implement RISC-V ISA compliance tests.
Perform functional coverage analysis and close coverage gaps.
Perform regression runs, analyze failures, and drive bug closure.
Connect simulations to real user interfaces, stimulus generators, and checkers.
Collaborate closely with RTL design engineers, architects, and software teams.
Contribute to the development and improvement of verification methodologies and automation scripts.
Perform preliminary debug of discovered issues.