SMTS Silicon Design Engineer
About The Position
AMD is hiring an SMTS Silicon Design Engineer to contribute to its CDFX DV team by performing DFT IP verification. The role includes creating and developing IP-level test plans, conducting and participating in test plan reviews, developing scalable verification components and random-constrained stimulus, and debugging regression failures. The engineer will perform code reviews and DV coverage analysis, provide technical guidance and ideas to improve quality, processes, and productivity, and lead DV execution, including project planning, delivery timelines, deliverables, and quality checks. The role also tracks project progress, provides technical support to internal SoC teams for DFT IP deliverables and tape-out readiness signoff, and collaborates with cross-functional DV technical leaders to drive DFX DV strategy. The position can be performed remotely. No travel is required.
Requirements
- A master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electrical and Electronics Engineering, or a related field, and four years of experience in the job offered or a closely related engineering role; alternatively, a bachelor’s degree or foreign equivalent in one of these fields and six years of progressive post-baccalaureate experience in the job offered or a closely related engineering role.
- Four years of experience in design verification on complex CPU/ASIC projects from inception to tape-out.
- Four years of experience in functional design verification, including test bench architecture, tool integration, coverage, power domains, random-constrained testing, and debugging.
- Four years of experience leading a small design verification engineering team.
- Four years of experience with IP-level test plan creation and development.
- Four years of experience conducting and participating in test plan reviews.
- Four years of experience developing scalable verification components.
- Four years of experience with random-constrained stimulus.
- Four years of experience debugging regression failures.
- Four years of experience with post-silicon debug and feedback integration into the design or verification flow.
- Four years of experience with code coverage closure.
Responsibilities
- Perform DFT IP verification as part of AMD’s CDFX DV team.
- Create and develop IP-level test plans and conduct or participate in test plan reviews.
- Develop scalable verification components and random-constrained stimulus.
- Debug regression failures.
- Perform code reviews and DV coverage analysis.
- Provide technical guidance and innovative ideas to improve quality, processes, and productivity.
- Lead DV execution, including project planning, delivery timelines, deliverables, and quality checks.
- Track project progress and help ensure timely completion.
- Provide technical support to internal SoC teams on DFT IP deliverables and tape-out readiness signoff.
- Collaborate with cross-functional DV technical leaders to drive DFX DV strategy.
Benefits
- AMD benefits are referenced as described in “AMD benefits at a glance”; specific benefits are not listed.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
