Signal and Power Integrity Technical Leader (Hybrid)

Cisco•Bismarck, ND

1d•$214,100 - $309,800

About The Position

Cisco Silicon One is hiring a Signal and Power Integrity Technical Leader to develop next-generation ASIC packaging and lead the Silicon Packaging Signal and Power Integrity Team. The team defines, designs, and verifies ASIC packaging for deployment across Cisco platforms, working with advanced IC package design and heterogeneous system integration technologies. The role develops and implements design rules for ultra-high-speed signaling; analyzes substrate signal and power integrity; and collaborates with layout teams on solutions spanning interposers, substrates, and PCBs. It designs and documents ASIC packages for high-volume release, including post-layout extraction and reporting, and works with system partners, vendors, and design leads to resolve complex technical issues. The Technical Leader defines processes, methods, and tools for complex ASIC and package development; contributes to chip architecture and high-performance ASIC design; mentors engineers; influences packaging and hardware teams; and promotes design reviews, postmortems, and continuous improvement. The position is based in Cisco’s San Jose office, with a preference for candidates able to commute onsite four to five days per week; fully remote candidates may also be considered.

Requirements

Bachelor’s degree in Electrical Engineering and at least 10 years of relevant signal and/or power integrity experience; or a Master’s degree in Electrical Engineering and at least 8 years; or a PhD in Electrical Engineering and at least 5 years.
Experience with multiple high-speed ASIC tape-outs from a package perspective.
Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics, including a solid understanding of scattering and impedance network parameters.
Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
Experience with SPICE.

Nice To Haves

Experience leading small to medium technical teams.
Ability to articulate ideas and technical concepts to diverse audiences, verbally and in writing.
Experience with advanced process nodes (5nm, 3nm, and below).
Experience with high-bandwidth memory (HBM) or high-speed memory interface signal integrity.
Experience with die-to-die interfaces such as UCIe or proprietary interfaces.
Experience with advanced packaging, including CoWoS, EMIB, and interposer-based designs, and signal and power integrity analysis of 2.5D ASIC packaging.
Experience with MATLAB or Python scripting.
Experience with Raptor-X.
Experience with Vector Network Analysis.
Experience with IBIS.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling while ensuring product power, performance, and area goals are met.
Analyze substrate signal integrity and power integrity, and collaborate with layout teams to develop solutions across interposer, substrate, and PCB designs.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and resolve complex technical issues using advanced technology design rules.
Define processes, methods, and tools for complex ASIC and package development.
Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
Mentor and support the signal integrity team and junior engineers, and influence packaging and hardware teams to meet technical specifications and develop innovative solutions.
Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.

Benefits

Medical insurance
Dental insurance
Vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
10 paid holidays per full calendar year
One floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
Four paid personal wellness days
Non-exempt employees receive 16 days of paid vacation per full calendar year, accrued at 4.92 hours per pay period for full-time employees
Exempt employees participate in a flexible vacation time-off program with no defined usage limit, subject to availability and business limitations
80 hours of sick time off provided on hire and each January 1, with up to 80 unused hours carried forward
Additional paid time away may be requested for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses may be available for non-sales roles