Sr. Verification Engineer
About The Position
Ambarella is seeking an experienced Senior Verification Engineer to lead verification of advanced SoCs incorporating image and video processing, DSP, CPUs, and neural network accelerators. The engineer will own verification strategies, develop scalable testbenches, drive coverage closure, and resolve complex design issues. The role uses and improves agentic AI verification flows in collaboration with internal AI experts to advance verification efficiency, quality, and automation. The engineer will work with architecture, RTL design, firmware, and software teams, and provide technical leadership through mentoring and review.
Requirements
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Typically 5+ years of ASIC or SoC verification experience, or equivalent expertise.
- Deep knowledge of SystemVerilog, UVM, constrained-random verification, assertions, and coverage methodologies.
- Experience architecting complex verification environments and driving coverage closure.
- Strong understanding of digital design, computer architecture, and SoC integration.
- Advanced RTL and system-level debugging skills.
- Strong programming skills in C/C++ and Python.
- Experience with commercial simulation, debugging, and coverage tools.
- Ability to independently lead verification projects and collaborate across teams.
Nice To Haves
- Experience verifying complex video, image processing, DSP, or AI accelerator SoCs.
- Knowledge of video compression, memory subsystems, and processor architectures.
- Hands-on experience with AI-assisted verification, LLMs, or agentic AI workflows.
- Experience improving verification automation, regression infrastructure, and simulation efficiency.
- Familiarity with AI agent frameworks and their integration into engineering workflows.
- Experience mentoring engineers and driving verification methodology improvements.
- Prior experience developing AI infrastructure is beneficial but not required.
Responsibilities
- Define and execute verification strategies and test plans for complex digital IP, subsystems, and SoCs.
- Architect and develop reusable verification environments using SystemVerilog, UVM, Verilog, C/C++, and Python.
- Lead verification of image processing pipelines, video input, compression engines including CABAC, DSP blocks, processor cores, and neural network accelerators.
- Develop constrained-random tests, reference models, assertions, scoreboards, and coverage models.
- Drive functional and code coverage closure and lead complex RTL and system-level debugging.
- Use, enhance, and extend agentic AI verification workflows for test generation, coverage analysis, failure triage, debugging, and regression automation.
- Collaborate with internal AI experts to identify opportunities to improve verification workflows and integrate new capabilities.
- Develop automation tools and optimize simulation and regression efficiency.
- Collaborate with architecture, RTL design, firmware, and software teams.
- Mentor junior engineers and interns, review verification deliverables, and provide technical leadership.
Benefits
- New-hire RSU grants.
- Opportunity for annual RSU grants.
- Other highly competitive benefits.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
