Verification Engineer II

Ambarella•Headquarters, KY

About The Position

We are seeking a talented and motivated Verification Engineer to join a semiconductor development team. The role involves verifying complex digital logic designs, developing testbenches, and contributing to the validation of next-generation video and image processing solutions. The engineer will help validate a complex media processor platform and key components including an image processing pipeline, video compression engine, and neural network vector processor. The position also involves collaborating with RTL design, architecture, and software teams to ensure thorough validation coverage.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or a related field (MSEE/M.S. CE required).
Strong hands-on experience with SystemVerilog and UVM methodology.
Solid understanding of digital design concepts and SoC architecture.
Proficiency in C/C++, scripting languages (Python and Perl), and simulation/debug tools.
Experience with functional and code coverage methodologies.
Excellent problem-solving and communication skills.

Nice To Haves

Knowledge of video compression and decompression algorithms, such as H.264 and H.265.
Familiarity with memory technologies and subsystems, including DDR4, LPDDR3, and LPDDR4.
Prior experience verifying large-scale media or image processing SoCs.

Responsibilities

Develop advanced testbenches using UVM, SystemVerilog, Verilog, C/C++, and scripting languages.
Create and execute test plans for digital signal processing blocks, control logic modules, and general-purpose processor cores.
Debug and validate a complex media processor platform using UVM, Verilog/SystemVerilog, C/C++, Python, and Perl.
Perform functional coverage analysis using industry-standard CAD tools.
Drive system-level verification of the image processing pipeline, video compression engine, and neural network vector processor.
Develop custom verification tools and scripts to streamline verification flows.
Collaborate with RTL design, architecture, and software teams to ensure thorough validation coverage.