Engineer II - Verification

Microchip Technology Inc. • Chandler, AZ

2d

About The Position

Join the dsPIC Microcontroller Business Unit’s IP Verification Engineering team to perform IP-level verification. The work includes verification architecture, testbench development, modeling, simulation, coverage, regressions, formal or dynamic simulation using UVM tests, debugging, signoff evidence, and lifecycle support. The role is suited to candidates with 2.5–5 years of relevant experience in these areas.

The engineer independently executes defined assignments and structured troubleshooting, partnering with architecture, design, product development, validation, and applications teams across the USA, India, and other global corporate teams. The goal is to deliver robust verification results, timely project execution, and continuous improvement.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, Engineering, or a related field.
• 2.5–5 years of relevant experience in design verification, UVM and/or formal testbench architecture, modeling, simulation, coverage, regression, debugging, signoff evidence, and lifecycle support.
• Demonstrated verification architecture, modeling, and simulation skills; UVM and formal testbench development; coverage analysis; structured debugging; AI/ML automation; technical documentation; and cross-functional influence.
• Demonstrated employment stability, reliability, and sustained accountability in prior roles.
• Effective teamwork and cross-functional collaboration.
• Integrity and accuracy in representing qualifications, experience, and credentials.

Nice To Haves

• Hands-on experience with UVM-based simulation and/or formal verification methodologies and tools.
• Strong proficiency in SystemVerilog, constrained-random verification, assertions, and coverage.
• Experience developing and maintaining IP-level and SoC-level verification environments.
• Experience with simulation, regression execution, coverage analysis, debug, verification signoff, and lifecycle support.
• Experience with verification automation and scripting using Python or Perl.
• Experience with AI-assisted technologies to improve verification productivity and quality and drive faster coverage closure.
• Strong understanding of digital design concepts, RTL fundamentals, and ARM or common SoC architectures.

Responsibilities

• Architect, develop, and maintain UVM-based verification environments and/or formal verification environments.
• Collaborate with architecture, design, validation, and applications teams to verify IP and product requirements.
• Develop and maintain verification plans, test strategies, and testbenches.
• Develop constrained-random tests and testbenches, assertions, and coverage; analyze coverage metrics and drive coverage closure.
• Develop formal properties, analyze proof results, and drive formal coverage closure.
• Configure, execute, and maintain UVM simulation and/or formal regressions.
• Debug RTL and testbench failures, perform root-cause analysis, and collaborate with design and architecture teams to resolve defects.
• Use AI-assisted and machine-learning-based automation to improve verification quality, accelerate development and debugging, and reduce verification cycle time.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level