SR Design Verification Engineer

Advanced Micro Devices, Inc•Santa Clara, CA

12h

About The Position

AMD’s Network Technologies Solutions Group (NTSG) provides advanced data center networking technology, including a high-performance DPU and software stack deployed across major cloud and enterprise environments. The Senior Design Verification Engineer will drive verification closure for complex, high-performance ASIC designs and contribute to next-generation AMD networking products. The role involves hands-on verification across IP, subsystem, and SoC levels in a fast-paced, collaborative environment.

Requirements

Expert-level knowledge of SystemVerilog and UVM.
Strong hands-on experience with SystemVerilog simulators; VCS is preferred.
Experience with waveform debuggers such as Verdi or DVE.
Proven experience verifying complex IP or subsystems using test plans, coverage, and constrained-random methodologies.
Strong debugging skills across architecture, RTL, and testbench layers.
Experience with industry protocols or components such as PCIe, AXI, Ethernet, DDR, or DMA engines.
Scripting skills in Python, Perl, Shell, Tcl, or an equivalent language for automation and infrastructure.
Strong analytical and problem-solving abilities, including a track record of debugging complex issues.
Ability to lead verification tasks independently and drive cross-team closure.
Excellent verbal and written communication skills.
Comfort working in a fast-paced, collaborative, multi-site environment.
Ability to mentor and guide junior design verification engineers.
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.

Nice To Haves

Experience with performance verification, power-aware verification (UPF), or formal verification.
Familiarity with FPGA/HAPS-based validation and acceleration flows.
Understanding of networking or high-speed I/O pipelines.
Exposure to architectural modeling or C/C++ reference models.
Master’s degree; preferred.

Responsibilities

Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
Create test plans, map features, and define coverage strategies for complex networking and data-path IP.
Develop SystemVerilog stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.
Own verification-plan execution, regression triage, and debugging of architectural, functional, and performance issues.
Root-cause failures across RTL, testbench, interfaces such as PCIe, DDR, and Ethernet, and system interactions.
Optimize simulations, coverage closure, and verification sign-off methodology.
Use simulation, debug, and analysis tools, including VCS, Verdi/DVE, coverage tools, and waveform analysis suites.
Improve verification methodology, automation, and infrastructure using tools such as Python, Tcl, and Make.
Collaborate with RTL design, architecture, validation, firmware, and emulation/HAPS teams.
Participate in design reviews and micro-architecture definition, bringing verification input into early design stages.
Mentor junior engineers and provide technical leadership within the verification team.