Senior Staff Digital Design Engineer

Credo•San Jose, CA

122d•$160,000 - $250,000•Onsite

About The Position

Credo is seeking a Senior Staff PHY RTL Design Engineer to develop advanced SerDes PHY Digital Signal Processing (DSP) blocks for next-generation networking, AI, data center, and high-performance computing products. The role covers RTL architecture, design, implementation, and verification. The engineer will work with system architects and algorithm teams to translate DSP algorithms into synthesizable RTL and support PHY integration, silicon bring-up, and system-level debugging. This position is onsite at Credo’s San Jose, California headquarters.

Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, with eight or more years of digital design experience, or equivalent expertise for senior candidates.
Strong RTL development skills using SystemVerilog, including fixed-point arithmetic RTL implementation.
Experience designing high-speed communication or DSP hardware.
Experience with the ASIC development flow, such as lint, CDC/RDC, synthesis, and timing analysis.
Familiarity with EDA tools from Synopsys, Cadence, or Siemens.
Strong debugging and problem-solving skills.

Nice To Haves

Experience with high-speed SerDes standards such as PCIe and Ethernet, and understanding of SerDes receiver and transmitter architectures.
Understanding of DSP algorithms such as LMS adaptation and timing recovery, with MATLAB or C/C++ modeling experience.
Familiarity with Python or other scripting languages.
Knowledge of mixed-signal PHY architecture and analog/digital interfaces, including experience with mixed-signal PHY simulations.
Experience supporting silicon bring-up and post-silicon validation, with exposure to advanced process nodes such as 7nm, 5nm, or 3nm and beyond.

Responsibilities

Define RTL micro-architecture for digital PHY and SerDes DSP functions.
Develop synthesizable RTL for DSP blocks, including FFE, DFE, adaptive equalization, and CDR loops, in collaboration with system architects and algorithm teams.
Optimize designs for performance, power, area, and latency.
Verify DSP modules and debug functional issues.
Support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
Analyze silicon bring-up data with validation teams to resolve issues.
Support PHY integration and system-level debugging.