Senior Staff ASIC Design Engineer

Credo•San Jose, CA
•$160,000 - $230,000

About The Position

As a Senior Staff ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to support successful tape-outs, and work closely with system teams on chip bring-up and validation. Credo develops fast, reliable, energy-efficient connectivity solutions. Its high-speed copper and optical interconnect products support data infrastructure demands for AI, with a portfolio that includes Active Electrical Cables, optical transceivers, memory solutions, retimers, DSPs, and diagnostic and analytics software.

Requirements

  • BS/MS in Electrical Engineering or a relevant field.
  • Ten or more years of ASIC design experience and a proven record of production tape-outs.
  • Strong digital logic design skills, including complex synchronous/asynchronous interfaces.
  • Proficiency in Verilog/SystemVerilog RTL.
  • Experience with high-speed Serdes design and familiarity with Ethernet (802.3) standards.
  • Knowledge of synthesis and static timing analysis.
  • Experience with testbench/test case development, gate-level simulation, chip bring-up, and validation.
  • UVM familiarity.

Nice To Haves

  • Scripting expertise in Python, Tcl, Perl, and/or Shell.
  • Familiarity with DFT methodology and the physical design flow.
  • Knowledge of PCIe, UALink, or AXI/CHI interfaces.
  • Hands-on STA and timing closure experience.

Responsibilities

  • Design, implement, and debug complex logic blocks and integrate IPs from internal and external vendors.
  • Support front-end integration tasks, including lint, CDC, synthesis, DFT, and ECO.
  • Participate in design and code reviews to ensure quality.
  • Develop testbenches and run RTL and gate-level simulations.
  • Partner with verification, DFT, physical design, software, firmware, and systems teams on tape-outs, chip bring-up, validation, and debug.
  • Collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs.

Benefits

  • Discretionary bonus
  • Equity
  • Medical and other benefits
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