Senior Staff ASIC Design Engineer

Credo•San Jose, CA

5d•$160,000 - $230,000

About The Position

As a Senior Staff ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation. The base salary range is $160,000–$230,000 per year. The offer depends on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity, and a full range of medical and other benefits. Credo describes its purpose as investing in meaningful projects and supporting employees’ career growth and lasting impact. The company emphasizes collaboration and an environment where people can do their best work. Its technology supports reliable, energy-efficient connections, and the team develops products and markets.

Requirements

BS or MS in Electrical Engineering or a relevant field.
Ten or more years of ASIC design experience.
Proven record of production tape-outs.
Strong digital logic design skills, including complex synchronous and asynchronous interfaces.
Proficiency in Verilog/SystemVerilog RTL.
Experience with high-speed SerDes design and familiarity with Ethernet (802.3) standards.
Knowledge of synthesis and static timing analysis.
Experience with testbench and test-case development; UVM familiarity.
Experience with gate-level simulation, chip bring-up, and validation.

Nice To Haves

Scripting expertise in Python, Tcl, Perl, and/or Shell.
Familiarity with DFT methodology and the physical design flow.
Knowledge of PCIe, UALink, or AXI/CHI interfaces.
Hands-on STA and timing-closure experience.

Responsibilities

Implement and verify RTL for complex logic blocks as part of front-end ASIC design.
Collaborate with PD, DFT, STA, and integration teams to support successful tape-outs.
Work with system teams on chip bring-up and validation.