Senior SoC HW Analog/Functional Validation Engineer

Microsoft•Hillsboro, OR
•$119,800 - $261,000

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops infrastructure and foundational technologies for Microsoft's online services and Azure platform. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages custom computer chips, including Azure Cobalt. The Cloud Compute Development Organization (CCDO) is seeking a Senior SoC HW Analog/Functional Validation Engineer for its post-silicon validation team, working on functional and/or power/performance validation across custom silicon projects. This technical individual contributor will own validation of PLL, IO electrical/analog, or functional IO interfaces; develop validation strategies, environments, tools, and methodologies; and execute, triage, and debug silicon validation content. The role also contributes to pre-silicon verification, improves designs and validation methods in collaboration with partner teams, and provides technical guidance and mentorship to engineers.

Requirements

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
  • Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
  • Must satisfy export-control eligibility requirements for access to controlled information; citizenship or qualifying status will be verified with valid documentation.
  • For the role's stated senior-level preferred profile: doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 3 years of technical engineering experience; or a master's degree in one of these fields and at least 6 years; or a bachelor's degree in one of these fields and at least 8 years; or equivalent experience.

Nice To Haves

  • Applied understanding of computer architecture and CPU/SoC validation principles, including SoC subsystem, SoC system-level, and platform-level functionality, and scripting or software development using industry-standard languages such as Python or C/C++.
  • Strong communication, collaboration, and teamwork skills, with the ability to lead, grow, and contribute to diverse and inclusive teams.
  • Experience in verification, logic development, analog validation, or validation tools as part of a CPU, SoC, and/or IP development team.
  • Demonstrated leadership skills.
  • Validation expertise in electrical areas such as SerDes, IO, high-speed interconnect, or analog circuits; power and performance; or automation, content creation, or tools/scripts development.
  • Ability to develop synthetic SoC validation content for core, coherency, memory, and IO, to run in bare-metal and OS environments.
  • Ability to develop sophisticated tools and scripts for SoC validation debug, such as maximum-power analysis, current-transient analysis, and register dumps.
  • Understanding of board-level schematics.
  • Understanding of system-level software and firmware.
  • Experience running silicon content on pre-silicon platforms such as emulation or FPGA.
  • Demonstrated success in hardware/software debug efforts.
  • Hands-on experience debugging silicon failures using on-chip debug features such as trace or JTAG and test equipment such as oscilloscopes, protocol analyzers, and bit-error-rate testers.

Responsibilities

  • Own post-silicon validation of PLL, IO electrical/analog, or functional IO interfaces.
  • Define, guide, and contribute to implementation of silicon debug tools and capabilities.
  • Develop expertise in high-speed IO interface architecture and implementation, including PLL, PCI, and CXL, and how interfaces interact with the SoC, platform, and software.
  • Provide technical guidance, coaching, and mentorship to other engineers.
  • Develop validation strategies, requirements, environments, tools, and methodologies, including debug board and hardware/software requirements.
  • Write test plans and develop test content, scripts, tools, and other validation collateral.
  • Execute post-silicon validation content and triage and debug failures.
  • Engage with partners to improve designs, validation plans and collateral, and methodologies to prevent, reduce, or detect bugs sooner and more reliably.
  • Collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers.
  • Deliver high-quality results on schedule and provide technical leadership with respect and integrity.
  • Contribute expertise to pre-silicon verification plans, tests, and debug for the assigned area.
  • Learn and adapt in a complex and dynamic environment.
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