Principal SoC HW Analog/Functional Validation Engineer

Microsoft•Hillsboro, OR

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops the infrastructure and foundational technologies that power Microsoft’s cloud services. Within SCHIE, the Compute Silicon & Manufacturing Engineering (CSME) organization is responsible for designing, developing, manufacturing, and packaging Microsoft computer chips, including Azure Cobalt. The Verification and Validation team helps ensure cloud hardware manufacturing quality, delivery, scale, and sustainability. The Cloud Compute Development Organization (CCDO) is seeking a Principal SoC HW Analog/Functional Validation Engineer for its post-silicon functional and/or power/performance validation team. The role contributes to custom SoC projects and focuses on validating areas such as PCIe, functional I/O, or electrical/analog interfaces. This is a high-impact technical individual contributor position that includes technical leadership, collaboration across engineering disciplines, and mentorship of other engineers. The engineer will develop validation strategies, requirements, environments, tools, and methodologies; create and execute test plans and validation content; and triage and debug silicon failures. The role also contributes expertise to pre-silicon verification planning, tests, and debug. The base pay range is USD $142,800–$274,800 per year across the U.S., with a different range of USD $188,000–$304,200 for specified San Francisco Bay Area and New York City metropolitan locations. Certain roles may be eligible for benefits and other compensation.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master’s degree in one of these fields and 6+ years of technical engineering experience; or a bachelor’s degree in one of these fields and 8+ years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Ability to meet export-control eligibility requirements; the successful candidate must provide proof of citizenship, U.S. residency, or other protected status, with citizenship verified using a valid passport or other applicable documentation.
Ability to develop synthetic SoC validation content for core, coherency, memory, and I/O to run in bare-metal and OS environments.
Ability to develop sophisticated tools and scripts for SoC validation debug, including maximum-power, current-transient, and register-dump activities.
Understanding of board-level schematics.
Understanding of system-level software and firmware.
Demonstrated success in hardware/software debug efforts.

Nice To Haves

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 5+ years of technical engineering experience; or a master’s degree in one of these fields and 8+ years of technical engineering experience; or a bachelor’s degree in one of these fields and 12+ years of technical engineering experience; or equivalent experience.
At least 1 year of experience working on or leading projects from beginning to end.
Applied understanding of computer architecture and CPU/SoC validation principles, including SoC subsystem, SoC system-level, and platform-level functionality.
Experience writing scripts or software in industry-standard languages such as Python or C/C++.
Strong communication, collaboration, and teamwork skills, with the ability to lead, grow, and contribute to diverse and inclusive teams.
Experience in verification, logic development, analog validation, or validation tools as part of a CPU, SoC, and/or IP development team.
Demonstrated leadership skills.
Validation expertise in one or more areas: functional I/O interfaces such as PCIe, CXL, or USB; electrical validation of SerDes, I/O, high-speed interconnects, or analog circuits; power and performance; automation; content creation; or tools and script development.
Experience running silicon content on pre-silicon platforms such as emulation or FPGA.
Hands-on expertise debugging silicon failures using on-chip debug features such as trace or JTAG and test equipment such as oscilloscopes, protocol analyzers, bit error rate testers, and logic analyzers.

Responsibilities

Own post-silicon validation for an area such as PCIe, functional I/O, or electrical/analog interfaces.
Define, guide, and contribute to implementation of silicon debug tools and capabilities.
Develop expertise in high-speed I/O interface architecture and implementation, including PCI and CXL, and understand interactions with the SoC, platform, and software.
Provide technical guidance, coaching, and mentorship to other engineers.
Develop validation strategy, requirements, environments, tools, and methodologies, including debug-board and hardware/software requirements.
Write test plans and implement them by developing test content, scripts, tools, and other validation collateral.
Execute post-silicon validation content and triage and debug failures.
Work with partners to improve designs, validation plans and collateral, and methodology to prevent, reduce, or find bugs sooner and more reliably.
Collaborate with and influence architects, logic designers, verification engineers, post-silicon validators, and IP and tool providers.
Deliver high-quality results on schedule and provide technical leadership with respect and integrity.
Apply expertise to pre-silicon verification plans, tests, and debug for the assigned area.