Senior SoC HW Analog/Functional Validation Engineer
About The Position
Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) organization builds infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. Within SCHIE, the Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages custom computer chips, including Azure Cobalt. Its Verification and Validation team supports the quality, delivery, scale, and sustainability of Microsoft cloud hardware. The Cloud Compute Development Organization is seeking a Senior SoC HW Analog/Functional Validation Engineer for its post-silicon functional and/or power/performance validation team. The engineer will own validation in an area such as PLL, IO electrical/analog, or functional IO interfaces, and contribute to custom SoC projects. The role includes developing validation strategies, requirements, environments, tools, and methodologies; creating and executing test plans and validation content; and triaging and debugging post-silicon failures. The engineer will collaborate across architecture, design, verification, validation, IP, and tool teams, guide other engineers, and contribute technical expertise to pre-silicon verification. The position requires passing Microsoft’s Cloud Background Check and meeting export-control eligibility requirements.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master’s degree in one of those fields and at least 4 years of experience; or a bachelor’s degree in one of those fields and at least 5 years of experience; or equivalent experience.
- Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
- Eligibility to access export-controlled information; the successful candidate must provide proof of citizenship, U.S. residency, or other protected status, with citizenship verified using a valid passport or other applicable documents for lawful permanent residents, refugees, and asylees.
- Applied understanding of computer architecture and CPU/SoC validation principles, including SoC subsystem-, system-, and platform-level functionality.
- Experience writing scripts or software in industry-standard languages such as Python or C/C++.
- Verification, logic development, analog validation, or validation tools experience on a CPU, SoC, and/or IP development team.
- Demonstrated validation expertise in one or more areas: electrical validation of SerDes, IO, high-speed interconnect, or analog circuits; power and performance; automation; content creation; or tools/scripts development.
- Ability to develop synthetic SoC validation content for core, coherency, memory, and IO to run in bare-metal and OS environments.
- Ability to develop sophisticated tools and scripts for SoC validation debug, such as maximum-power analysis, current transients, and register dumps.
- Understanding of board-level schematics, system-level software, and firmware.
- Demonstrated success in hardware/software debug efforts.
- Proficient communication, collaboration, and teamwork skills, including ability to lead, grow, and contribute to diverse and inclusive teams.
- Demonstrated leadership skills.
Nice To Haves
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 3 years of technical engineering experience; or a master’s degree in one of those fields and at least 6 years of experience; or a bachelor’s degree in one of those fields and at least 8 years of experience; or equivalent experience.
- Experience running silicon content on pre-silicon platforms such as emulation or FPGA.
- Hands-on expertise debugging silicon failures using on-chip debug features such as trace or JTAG and test equipment such as oscilloscopes, protocol analyzers, bit-error-rate testers, or logic analyzers.
Responsibilities
- Own post-silicon validation for PLL, IO electrical/analog, or functional IO interfaces.
- Define, guide, and contribute to implementation of silicon debug tools and capabilities.
- Develop expertise in high-speed IO interface architecture and implementation, including PLL, PCI, and CXL, and their interactions with the SoC, platform, and software.
- Provide technical guidance, coaching, and mentorship to other engineers.
- Develop validation strategy, requirements, environments, tools, and methodologies, including debug-board and hardware/software requirements.
- Write test plans and implement them by developing test content, scripts, tools, and other validation collateral.
- Execute post-silicon content and triage and debug failures.
- Engage with partners to improve designs, validation plans and collateral, and methodologies to prevent, reduce, or find bugs sooner and more reliably.
- Collaborate with architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers.
- Deliver high-quality results on schedule and provide technical leadership with respect and integrity.
- Contribute expertise to pre-silicon verification plans, tests, and debug for the engineer’s area.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
