Senior SoC Validation Engineer

Cynet Systems • San Jose, CA

1d

About The Position

We are seeking a senior-level contractor to lead production test development for SoC devices integrating copackaged optics (CPO) SerDes interfaces. The role focuses on ATE program development, DFT/BIST enablement, yield and quality optimization, and high-volume manufacturability. It requires a strong understanding of SerDes and protocols such as UCIe and PCIe, particularly translating characterization results into robust multisite production tests. Python-based automation and data analytics are essential; familiarity with AI-assisted tools for test development and data triage is a plus.

The engineer will develop, integrate, and maintain wafer-sort and final-test programs; define production test coverage for SerDes PHY and protocol features; optimize multisite test strategies and test time; correlate bench and characterization results with ATE; integrate DFT features into production flows; and build automation and analytics tooling. The role also involves collaboration across engineering and manufacturing teams, documentation, operations training, and sustaining engineering support.

Requirements

• Hands-on experience developing on leading ATE platforms, such as Advantest V93K/AC+ or Teradyne UltraFLEX/UltraFLEXplus, including timing sets, DC/AC measurements, and multisite.
• Strong understanding of SerDes/PHY fundamentals, including equalization, CDR, CTLE/DFE, PRBS/BER, margining, jitter/eye constraints, and on-die BIST integration.
• Proficiency in Python for automation and data analytics.
• Experience with STDF parsing, visualization, and automated SPC/anomaly detection.
• Solid DFT background, including scan/ATPG patterns, boundary scan, MBIST/LBIST, JTAG access, WGL/STIL pattern formats, and pattern bring-up on ATE.
• Working knowledge of UCIe and PCIe from a production-test perspective, including link checks via firmware/test hooks, error counters, and compliance indicators.
• Excellent documentation, cross-functional communication, and problem-solving skills.

Nice To Haves

• Familiarity with AI-assisted tools for test development and data triage.
• UCIe and PCIe Gen5/Gen6 experience is preferred.

Responsibilities

• Own development, integration, and maintenance of wafer-sort and final-test ATE programs for SoC SerDes with copackaged optics.
• Define and implement production test coverage for SerDes PHY and protocol features, including PRBS, loopback, margining, FEC, CDR lock, and EQ settings, using on-die BIST/DFT and ATE instrumentation.
• Implement and optimize multisite strategies, parallel test execution, guardbanding, and test-time reduction while meeting quality and coverage goals.
• Correlate bench and characterization results to ATE; develop golden-unit flows, establish limits, create characterization-to-production handoffs, and close gaps.
• Integrate scan/ATPG, boundary scan, MBIST/LBIST, and JTAG DFT features into production flows; manage pattern conversion, timing sets, and pin maps.
• Implement UCIe/PCIe-related production checks, including link-training emulation, LTSSM state verification via firmware or test hooks, compliance counters, and error injection and monitoring.
• Build Python-based tooling for ATE control, data parsing, STDF analytics, dashboards, and automated limit updates; integrate with MES/SPC and CI pipelines.
• Collaborate with silicon design, firmware, DFT, product engineering, OSAT/probe, and SI teams to resolve issues and qualify ECOs/revisions.
• Document test plans, specifications, vector maps, limits, and release notes; train operations teams and support sustaining engineering.

What This Job Offers

• Career Level: Senior
• Education Level: No Education Listed