Senior Principal Verification Engineer

Microsoft•Raleigh, NC

2d•$165,600 - $296,400

About The Position

Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) organization powers Microsoft’s Intelligent Cloud mission. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages computer chips, including Azure Cobalt, and supports the quality, delivery, scale, and sustainability of Microsoft cloud hardware. The Senior Principal Verification Engineer will support this work by leading SoC design verification strategy and execution for complex designs, helping deliver high-quality silicon on schedule and at scale. The role provides senior technical leadership for SoC verification architecture, methodology, infrastructure, and best practices. It covers verification of critical SoC functions and system-level scenarios, including complex subsystem interactions, concurrency, stress conditions, error handling, and recovery. The engineer will collaborate across architecture, RTL design, firmware, performance, emulation, validation, IP verification, and other teams, while identifying risks and coverage gaps and mentoring engineers. Candidates must meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check. The position involves access to export-controlled information, and the successful candidate must provide citizenship or qualifying residency/protected-status documentation for eligibility assessment. Citizenship will be verified with a valid passport; other documents may apply for lawful permanent residents, refugees, and asylees. The listed U.S. base pay range is $165,600–$296,400 per year, with a range of $220,800–$331,200 for specified locations in the San Francisco Bay Area and New York City metropolitan area. Certain roles may be eligible for benefits and other compensation. The position will be open for at least five days, with applications accepted until it is filled.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 7+ years of technical engineering experience; or a master’s degree in one of these fields and 10+ years of experience; or a bachelor’s degree in one of these fields and 12+ years of experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Must provide proof of citizenship, U.S. residency, or other qualifying protected status to establish eligibility for access to export-controlled information; citizenship is verified with a valid passport, with other applicable documents permitted for lawful permanent residents, refugees, and asylees.
10+ years of functional verification experience in complex CPU, SoC, or IP development environments.
Experienced SystemVerilog/UVM skills and working knowledge of C/C++ and scripting languages.
Demonstrated ability to drive complex technical problems across architecture, design, firmware, performance, and verification teams.
Strong communication and collaboration skills, with the ability to provide technical leadership and contribute effectively across diverse cross-functional teams.

Nice To Haves

Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
At least 8 years acting in a technical lead capacity managing complex cross-functional or cross-geographic silicon verification projects.
Demonstrated technical depth in one or more of: ARM/CPU architecture; memory subsystem architecture, memory controllers/PHYs, and DDR protocols; coherent/non-coherent fabrics and protocols; PCIe/CXL controllers, PHYs, and protocols; or IOMMU/SMMU, address translation, and virtualization.

Responsibilities

Define and drive SoC verification architecture, strategy, and methodology for complex multi-IP and multi-subsystem designs.
Develop comprehensive verification plans based on architecture, specifications, use cases, and potential system-level failure scenarios.
Lead verification of critical SoC functionality, including interconnect, coherency, memory, I/O, security, power management, reset, debug, and system-level flows.
Drive development of scalable verification environments, stimulus, checkers, scoreboards, assertions, functional coverage, and verification infrastructure.
Identify verification gaps, architectural corner cases, and cross-IP interactions not adequately covered by block- or subsystem-level verification.
Partner with architecture, RTL design, firmware, performance, emulation, validation, and IP verification teams to ensure end-to-end verification coverage.
Lead verification of system-level scenarios, concurrency, stress conditions, error handling, recovery, and complex interactions across multiple subsystems.
Influence verification methodology and infrastructure improvements to increase coverage, productivity, scalability, debug efficiency, and quality.
Identify verification risks early and drive mitigation plans to protect program quality and schedule.
Participate in architecture, design, test-plan, coverage, and verification-readiness reviews.
Serve as a senior technical authority for SoC design verification and establish verification best practices and technical direction across projects.
Provide technical guidance and mentorship to verification engineers across the organization.
Collaborate with and influence architects, logic designers, post-silicon validators, verification engineers, and IP and tool providers.