Principal Physical Verification Engineer

Celero Communications • Irvine, CA

2d

About The Position

The Principal Physical Verification Engineer leads full-chip physical verification, including planning and executing verification schedules, conducting full-chip and block-level checks, and driving quality, milestone, and tapeout readiness. The role owns full-chip verification and works with internal analog teams to support clean IP delivery. It includes running and analyzing DRC, ERC, LUP, and PERC results using ICV or Calibre tools, with an understanding of advanced TSMC DRC rules.

The engineer collaborates with analog, block, and chip-top owners to support clean floorplans, provide early guidance on corner-case requirements, influence floorplan constraints, hierarchy, and implementation strategy, and participate in tapeout readiness reviews.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.
• 7+ years of experience with full-chip verifications.
• Hands-on experience with a Physical Verification tool such as ICV or Calibre.
• Ability to assemble a flow to support block- or chip-level Physical Verification.
• Strong expertise in floorplanning to avoid DRC/LVS issues.
• Ability to guide the analog IP team to enable clean integration.
• Understanding of advanced TSMC DRC rules.

Nice To Haves

• Experience with advanced technology nodes such as 7nm, 5nm, or 3nm.
• Automation skills using Tcl, Python, or shell scripting.

Responsibilities

• Lead the full-chip Physical Verification effort.
• Own execution plans and schedules for full-chip verification.
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full-chip and block-level Physical Verification checks.
• Own full-chip verification.
• Work with the internal analog team to ensure clean IP delivery.
• Run and analyze DRC, ERC, LUP, and PERC results.
• Partner with analog, block, and chip-top owners to ensure a clean floorplan.
• Provide early guidance on corner-case requirements.
• Influence floorplan constraints, hierarchy, and implementation strategy.
• Participate in tapeout readiness reviews.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal