Senior Principal Verification Engineer

Microsoft•Raleigh, NC

2d•$165,600 - $331,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s expanding cloud infrastructure and supports its Intelligent Cloud mission. The Compute Silicon & Manufacturing Engineering organization within SCHIE designs, develops, manufactures, and packages computer chips, including Azure Cobalt. The team works to deliver cloud hardware at scale with high quality, timely delivery, and sustainability in mind. The Senior Principal Verification Engineer will provide technical leadership for verification of complex SoCs. The role defines verification architecture, strategy, and methodology; leads verification of critical system functionality and cross-subsystem scenarios; and develops scalable verification environments and infrastructure. The engineer partners across architecture, RTL design, firmware, performance, emulation, validation, and IP verification teams, identifies risks and coverage gaps, and guides verification engineers across the organization.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 7+ years of technical engineering experience; or a master’s degree in one of these fields and 10+ years of experience; or a bachelor’s degree in one of these fields and 12+ years of experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Ability to meet export-control eligibility requirements; the successful candidate must provide proof of citizenship, U.S. residency, or other protected status, with citizenship verified using a valid passport or applicable status documents.
Demonstrated technical depth in one or more of the following: ARM/CPU architecture; memory subsystem architecture, memory controllers/PHYs, and DDR protocols; coherent/non-coherent fabrics and protocols; PCIe/CXL controllers, PHYs, and protocols; or IOMMU/SMMU, address translation, and virtualization.
Experienced SystemVerilog/UVM skills and working knowledge of C/C++ and scripting languages.
Ability to drive complex technical problems across architecture, design, firmware, performance, and verification teams.
Communication and collaboration skills, with the ability to provide technical leadership and contribute across diverse, cross-functional teams.

Nice To Haves

BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related degree.
At least 8 years acting in a technical lead capacity managing complex cross-functional or cross-geographic silicon verification projects.
10+ years of functional verification experience in complex CPU, SoC, or IP development environments.

Responsibilities

Define and drive the SoC verification architecture, strategy, and methodology for complex multi-IP and multi-subsystem designs.
Develop comprehensive verification plans based on architecture, specifications, use cases, and potential system-level failure scenarios.
Lead verification of critical SoC functionality, including interconnect, coherency, memory, I/O, security, power management, reset, debug, and system-level flows.
Drive development of scalable environments, stimulus, checkers, scoreboards, assertions, functional coverage, and verification infrastructure.
Identify verification gaps, architectural corner cases, and cross-IP interactions that may not be adequately covered by block- or subsystem-level verification.
Partner with architecture, RTL design, firmware, performance, emulation, validation, and IP verification teams to ensure end-to-end verification coverage.
Lead verification of system-level scenarios, concurrency, stress conditions, error handling, recovery, and complex interactions across multiple subsystems.
Influence verification methodology and infrastructure improvements to increase coverage, productivity, scalability, debug efficiency, and quality.
Identify verification risks early and drive mitigation plans to protect program quality and schedule.
Participate in architecture, design, test-plan, coverage, and verification readiness reviews.
Serve as a senior technical authority for SoC DV and help establish verification best practices and technical direction across projects.
Provide technical guidance and mentorship to verification engineers across the organization.
Collaborate with and influence architects, logic designers, post-silicon validators, verification engineers, and IP and tool providers.
Embody Microsoft’s culture and values.