Senior Principal Design Verification Engineer

Microsoft • Redmond, WA

3d • $165,600 - $331,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) builds and operates the infrastructure and foundational technologies supporting Microsoft’s online businesses and Azure platform. The AI Silicon Engineering (AISiE) SoC Design Verification team verifies Microsoft’s AI accelerators in partnership with systems, firmware, architecture, design, validation, and product engineering teams.

The Senior Principal Design Verification Engineer will architect and drive complex pre-silicon verification, including SoC security verification, for AI accelerators. The work spans block, chip, and system levels through post-silicon validation, and includes developing verification environments and tests, planning and executing feature coverage, and addressing quality and design challenges. The role also collaborates across teams and geographies using Agile development practices.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 7 or more years of technical engineering experience; or a master's degree in one of these fields and 10 or more years of technical engineering experience; or a bachelor's degree in one of these fields and 12 or more years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• For access to export-controlled information, provide proof of citizenship, U.S. permanent residency, or other protected status as required; citizenship will be verified with a valid passport, with other documents accepted for lawful permanent residents, refugees, and asylees where applicable.

Nice To Haves

• CPU, graphics, or NPU security architecture or micro-architecture experience.
• Experience architecting confidential computing solutions for workload isolation, memory protection and encryption, trusted execution, attestation, and data-in-use protection.
• Experience owning hardware security microarchitecture, including key management, cryptography, secure storage, anti-rollback, access control, and hardware trust boundaries.
• Experience driving end-to-end SoC security across compute, memory, I/O, chip-to-chip interfaces, firmware, and accelerators.
• Ability to apply verification principles, testbench architectures, and scalable stimulus generation to enable comprehensive security verification.
• Experience partnering across RTL, firmware, DV, PD, platform, and security teams on threat analysis, security verification, vulnerability closure, and silicon signoff.

Responsibilities

• Create complex verification environments and tests, driving pre-silicon functional verification at block, chip, and system levels, reference modeling, and post-silicon validation.
• Work with architects and design engineers to develop verification plans covering strategy, test environments, tests, and requirements for IP, subsystem, and SoC verification; drive test plans and test development to provide feature coverage.
• Define SoC security architecture and threat models, including secure boot, root of trust, identity, isolation, privilege, debug, lifecycle, and recovery.
• Develop verification components such as scoreboards, sequences, constraints, assertions, and functional coverage, as well as Makefiles and scripts for scalable verification.
• Develop and implement technical solutions to complex quality and design challenges, and triage and debug testbench, simulation, and emulation failures.
• Apply Agile development methodologies, including code reviews, sprint planning, and frequent deployment, and collaborate with teams across sites and geographies.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior