Principal Design Verification Engineer

Microsoft•Raleigh, NC

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s expanding cloud infrastructure and supports the Intelligent Cloud mission. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages Microsoft computer chips, including Azure Cobalt. Its Verification & Validation team helps define and deliver operational measures of success for hardware manufacturing, with a focus on quality, delivery, scale, and sustainability. The Principal Design Verification Engineer will lead or own functional or performance verification of aspects of Fabric Top subsystem integration, including coherency, traffic to and from memory and PCIe/CXL endpoints, and end-to-end interconnect functionality. The role partners with architecture, design, and verification teams to establish verification strategies and signoff criteria, develops UVM and/or Formal environments and reusable tools, drives bug discovery and root-cause analysis, improves productivity through automation and AI-driven solutions, and mentors engineers.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or Master's degree in one of these fields and 6+ years of experience; or Bachelor's degree in one of these fields and 8+ years of experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Ability to satisfy export-control access eligibility requirements, including providing proof of citizenship, U.S. residency, or other protected status; citizenship will be verified with a valid passport, with other documents applicable for lawful permanent residents, refugees, and asylees.

Nice To Haves

Experience with one or more of fabric interconnects, coherency, CHI, AMBA, PCIe, CXL, protocol bridges, or memory subsystems.
Experience architecting and developing UVM verification environments, assertions, checkers, and coverage models.
Experience driving IP verification for multiple product cycles from definition to silicon, including writing IP/block or subsystem-level test plans, developing tests, debugging failures, and coverage signoff.
Demonstrated hands-on technical leadership, such as creating bottom-up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems.
Experience with Formal Verification and assertion-based verification methodologies.
Proficiency with Python or similar scripting languages for automation and data analysis.
Experience applying AI-assisted tools to engineering and verification workflows.

Responsibilities

Own or lead functional or performance verification of one or more aspects of Fabric Top subsystem integration, including coherency, traffic flows to and from memory and PCIe/CXL endpoints, and end-to-end interconnect functionality.
Partner with architecture, design, and verification teams to define verification strategies, test plans, and signoff criteria.
Develop and enhance UVM and/or Formal verification environments, performance measurement tools, automation infrastructure, and reusable collateral.
Drive bug discovery and root-cause analysis through simulation, formal analysis, assertions, coverage, and debug.
Improve verification productivity through automation, methodologies, and AI-driven solutions.
Coach and mentor engineers in verification methodologies and best practices.
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.