Principal Physical Verification Engineer

Celero Communications • San Jose, CA

2d

About The Position

The Lead/Principal Full-Chip Physical Verification Engineer leads full-chip physical verification, owns execution plans and schedules, and drives quality, milestone accountability, and tapeout readiness. The role conducts full-chip and block physical verification checks and owns full-chip verification activities.

The engineer works with the internal analog team to ensure clean IP delivery and runs and analyzes DRC, ERC, LUP, and PERC results using ICV or Calibre verification tools. The role collaborates with analog, block, and chip-top owners to support clean floorplanning, provide early guidance on corner-case requirements, influence floorplan constraints, hierarchy, and implementation strategy, and participate in tapeout readiness reviews.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.
• 7+ years of experience with full-chip verifications.
• Hands-on experience with Physical Verification tools such as ICV or Calibre.
• Ability to assemble a flow to support block- and chip-level Physical Verification.
• Strong expertise in floorplanning to avoid DRC/LVS issues.
• Ability to guide the analog IP team to allow for clean integration.
• Understanding of advanced TSMC DRC rules.

Nice To Haves

• Experience with advanced technology nodes such as 7nm, 5nm, or 3nm.
• Automation skills using Tcl, Python, or shell scripting.

Responsibilities

• Lead the full-chip Physical Verification effort.
• Own execution plans and schedules for full-chip verification.
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full-chip and block Physical Verification checks.
• Own full-chip verification activities.
• Work with the internal analog team to ensure clean IP delivery.
• Run and analyze DRC/ERC/LUP/PERC results.
• Partner with analog, block, and chip-top owners to ensure clean floorplanning.
• Provide early guidance on corner-case requirements.
• Influence floorplan constraints, hierarchy, and implementation strategy.
• Participate in tapeout readiness reviews.
• Assemble a flow to support block- and chip-level Physical Verification.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal