RTL-to-GDS implementation, Senior Principal Solutions Engineer

Cadence Systems • Austin, TX

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About The Position

The Senior Principal Solutions Engineer supports adoption of Cadence products to help chip designer customers achieve their design performance, power, and area goals. The role requires expertise in synthesis, especially physical synthesis, place and route, static timing analysis, and SDC, as well as experience supporting tapeouts. Experience with multivoltage design implementation and clock-tree debugging is desirable.

Solutions Engineers articulate design methodologies involving Cadence tools and communicate effectively across the Cadence tool portfolio. The role includes developing expertise in additional or specialized tools, broadening from product emphasis to methodology, completing full-flow implementation training, and learning to leverage successful implementations. Full Flow Services projects involve owning block and top-level implementation and signoff-focused work, with exposure to RTL-to-GDSII project delivery. There are also opportunities to participate in competitive benchmarking on complex blocks such as CPUs, GPUs, and DSP cores, across multiple technology nodes using standard foundry solutions.

The position works with leading-edge wireless and mobile customers on low-power and multivoltage design techniques. It also includes managing strategic customer evaluations and benchmarks for Cadence front-end solutions to demonstrate technology differentiation and Cadence’s competitive advantages.

Requirements

• 7+ years of experience.
• Strong technical knowledge of company products.
• ASIC design experience using industry-standard hardware description languages, including Verilog.
• Deep knowledge and experience with Cadence or Synopsys place-and-route tools, including physical synthesis, PnR, CTS, and static timing analysis.
• Experience with synthesis, place and route, STA/SDC, and supporting tapeouts.
• Ability to articulate design methodologies involving Cadence tools and communicate across the Cadence tool portfolio.
• Ability to manage multiple issues, set priorities, and exploit new technologies.

Nice To Haves

• Experience with multivoltage design implementation.
• Experience with clock-tree debugging.

Responsibilities

• Support adoption of Cadence products to help chip designer customers achieve design PPA goals.
• Support RTL-to-GDS implementation, including synthesis, place and route, static timing analysis, and SDC-related work.
• Support tapeouts and participate in block implementation, top-level implementation, and signoff-focused Full Flow Services projects.
• Articulate design methodologies involving Cadence tools and communicate across the Cadence tool portfolio.
• Develop expertise in additional or specialized tools, broaden focus from products to methodology, and complete full-flow implementation training.
• Participate in competitive benchmarking on complex blocks such as CPUs, GPUs, and DSP cores across multiple technology nodes.
• Work with leading-edge wireless and mobile customers on low-power and multivoltage design techniques.
• Manage strategic customer evaluations and benchmarks on Cadence front-end solutions to establish technology differentiation and competitive advantages.
• Multiplex several issues, set priorities, and exploit new technologies.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed