RTL-to-GDS implementation, Senior Principal Solutions Engineer

Cadence Design Systems•Austin, TX

10d

About The Position

The Senior Principal Solutions Engineer supports adoption of Cadence products to help chip designer customers achieve their design performance, power, and area goals. The role focuses on place-and-route implementation, with additional expertise in logical and physical synthesis, static timing analysis, and SDC. The engineer supports tapeouts and helps customers apply Cadence tools and methodologies to RTL-to-GDSII projects. The position includes developing expertise in additional or specialized tools, broadening product knowledge into methodology, completing full-flow implementation training, and learning to leverage successful implementations. Full-flow services work may involve owning block and top-level implementation as well as signoff-focused efforts. The role offers exposure to projects across multiple technology nodes using standard foundry solutions, and opportunities to participate in competitive benchmarking on complex CPU, GPU, and DSP blocks. The engineer also supports customer evaluations and benchmarks of Cadence front-end solutions and helps establish technology differentiation and competitive advantages.

Requirements

7+ years of experience.
Strong technical knowledge of company products.
ASIC design experience using industry-standard hardware description languages, including Verilog.
Deep knowledge of Cadence or Synopsys place-and-route tools.
Experience and knowledge in physical synthesis, place and route, clock tree synthesis, and static timing analysis.
Experience supporting RTL-to-GDS implementation flows using the Encounter Digital Implementation Platform.
Ability to manage multiple issues, set priorities, and exploit new technologies.

Nice To Haves

Experience with multivoltage design implementation.
Experience with clock tree debugging.
Some experience supporting tapeouts.

Responsibilities

Support adoption of Cadence products to help chip designer customers achieve design PPA goals.
Support design implementation activities including synthesis, place and route, static timing analysis, and SDC.
Support tapeouts and articulate design methodologies involving Cadence tools.
Develop expertise in additional or specialized tools and broaden product-focused knowledge into methodology and full-flow implementation.
Own block implementation, top-level implementation, and signoff-focused efforts on full-flow services projects.
Work on RTL-to-GDSII delivery projects across multiple technology nodes using standard foundry solutions.
Participate in competitive benchmarking on complex blocks, including CPUs, GPUs, and DSP cores.
Innovate with low-power and multi-voltage design techniques for wireless and mobile customers.
Manage strategic customer evaluations and benchmarks on Cadence front-end solutions to demonstrate technology differentiation and Cadence's competitive advantages.
Multiplex several issues, set priorities, and exploit new technologies.