RTL Engineer – Physical AI Solutions

Altera•San Jose, CA

2d•$149,100 - $238,200

About The Position

Altera is seeking an RTL Engineer to develop next-generation hardware architectures that accelerate Physical AI workloads. The role focuses on FPGA and heterogeneous compute solutions for applications such as robotics, autonomous systems, machine vision, industrial automation, and real-time AI inference. The engineer will design, implement, and verify high-performance digital logic for AI and accelerated computing solutions. The role collaborates with architecture, design verification, software, firmware, and physical design teams to deliver scalable and efficient hardware for advanced FPGA and programmable logic platforms. It includes translating architectural specifications into synthesizable RTL, optimizing designs, supporting FPGA implementation and system bring-up, and debugging issues throughout the product lifecycle. The Bay Area, California pay range is $149,100–$238,200 USD. Actual salary may vary based on factors including location, job-related knowledge, skills, experience, and training. Incentive opportunities are also offered based on individual and company performance. Applicants must be eligible for any required U.S. export authorizations. The employer uses artificial intelligence to screen, assess, or select applicants.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
At least 3 years of experience in RTL design and digital logic development.
Strong expertise in Verilog and/or SystemVerilog.
Solid understanding of computer architecture, digital design fundamentals, and ASIC/FPGA design methodologies.
Experience with simulation, debugging, and verification tools.
Experience developing high-performance datapath, control logic, or accelerator architectures.
Familiarity with synthesis, static timing analysis, and FPGA implementation flows.
Strong analytical, debugging, and problem-solving skills.
Excellent communication and collaboration abilities.
Eligibility for any required U.S. export authorizations.

Nice To Haves

Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline.
Experience designing AI, machine learning, vision-processing, signal-processing, networking, or robotics accelerators.
Knowledge of FPGA architectures and adaptive computing platforms.
Experience with industry-standard EDA tools such as Synopsys, Siemens EDA, or Cadence design environments.
Understanding of high-bandwidth memory systems, NoC architectures, PCIe, Ethernet, CXL, or coherent interconnects.
Experience with hardware/software co-design.
Familiarity with Python, C/C++, or scripting languages used for design automation and validation.
Experience developing solutions for robotics, industrial automation, autonomous systems, or edge AI applications.

Responsibilities

Design and develop RTL for FPGA and programmable hardware solutions supporting Physical AI applications.
Translate architectural specifications into high-quality, synthesizable Verilog/SystemVerilog RTL.
Create microarchitecture specifications and participate in architecture reviews.
Optimize designs for performance, area, power, and scalability.
Collaborate with design verification teams to define verification strategies and close functional coverage.
Support FPGA implementation activities, including synthesis, timing closure, and performance analysis.
Work with firmware and software teams to enable hardware-software integration and system bring-up.
Debug RTL, simulation, emulation, and silicon-related issues throughout the product lifecycle.
Contribute to feature definition and architectural innovation for next-generation AI acceleration technologies.
Participate in design reviews and maintain high standards for code quality and engineering excellence.