Senior Principal Digital SoC Design Engineer

MaxLinear, Inc.•San Jose, CA

15h•$200,000 - $250,000

About The Position

MaxLinear is seeking a Senior Principal Digital SoC Design Engineer for its Analog Mixed Signal (AMS) group in San Jose, California. The AMS team develops integrated solutions for high-speed and embedded connectivity interfaces, including bridges, serial transceivers, and isolators, as well as power management products for data center, industrial, and embedded platforms. The role leads digital architecture and RTL across a product roadmap that includes USB connectivity bridges, PCIe-to-USB host bridge devices, and complex embedded-processor SoCs for data center platform management. The engineer will drive architecture, integration, quality, verification planning, and product development from concept through silicon bring-up, compliance, qualification, and production. They will also mentor senior engineers, lead design reviews, and serve as the digital technical authority across the connectivity and SoC roadmap.

Requirements

Deep hands-on expertise in SystemVerilog/Verilog RTL design, SoC micro-architecture, and complex top-level integration.
Strong working knowledge of USB 2.0/3.x device and host architectures, including xHCI, and PCIe endpoint architecture; experience integrating licensed controller and PHY IP.
Experience with UART, I²C/I3C, SPI, and GPIO interfaces, as well as bridge-type data paths, FIFOs, and DMA.
Experience integrating embedded Arm processor subsystems, DDR/memory controllers, AMBA AXI/AHB/APB bus fabrics, and security IP.
Strong understanding of clock/reset, CDC/RDC, low-power design, timing constraints, synthesis, DFT, and physical-design trade-offs.
Track record delivering multiple SoCs from architecture through tapeout, silicon bring-up, compliance certification, and high-volume production.
Experience working with external design partners and IP vendors, with the ability to lead technically across multiple disciplines and global teams.
BS in Electrical Engineering or a related field plus 15 years of experience, or MS plus 12 years of experience, or Ph.D. plus 9 years of experience.

Nice To Haves

Familiarity with data center server management concepts such as eSPI, I3C, MCTP, and hardware root of trust.

Responsibilities

Lead digital architecture and RTL for USB device-side connectivity bridges, including multi-port UART, I²C/SPI/GPIO bridging, endpoint and FIFO architecture, flow control, and OTP-based configurability and customization.
Architect and integrate PCIe-to-USB host bridge solutions, including PCIe endpoints, USB host controller (xHCI) integration, DMA engines, buffer management, interrupt and power-state handling, and driver-visible register architecture.
Define and lead digital architecture for embedded-processor SoCs for data center platform management, including multi-core Arm subsystems, memory controllers, high-speed host interfaces, sideband management buses, and peripheral-rich I/O.
Drive platform security and management features, including secure boot, hardware root of trust, cryptographic checksum generation and checking, and host-to-management communication paths.
Maximize reuse of digital IP across product generations and guide make, reuse, or license decisions for USB, PCIe, and other interface controllers and PHYs.
Define on-chip interconnect, clock/reset, low-power, and DFT architecture, and own RTL quality through lint, CDC/RDC, synthesis, timing constraints, and implementation closure.
Set verification strategy with the design verification team, including compliance and interoperability readiness, emulation/FPGA prototyping, and firmware/driver co-verification.
Partner with analog/mixed-signal, PHY, firmware, software, package, test, and applications teams from concept through silicon bring-up, compliance, qualification, and production.
Mentor senior engineers, lead design reviews, and act as the digital technical authority across the connectivity and SoC roadmap.