SoC Design Engineer

Solidigm•San Jose, CA

3d•$167,360 - $267,800

About The Position

Solidigm is seeking an experienced RTL Design Engineer to drive the architecture, design, implementation, and optimization of complex digital logic for next-generation NAND Flash memory-based SSD controllers. The role translates system-level requirements into microarchitecture and synthesizable RTL, balances performance, power, and area (PPA), and delivers designs through ASIC implementation and silicon validation. The engineer works with architecture, firmware, verification, physical design, NAND technology, and validation teams to develop scalable, reliable controller solutions. The position covers the SoC design flow from architecture and RTL through synthesis, integration, timing and power optimization, implementation handoff, and support for pre-silicon and post-silicon activities. It includes NAND controller functionality, data integrity and reliability logic, and technical collaboration and leadership. Compensation is $167,360–$267,800 yearly. The role is eligible for restricted stock unit, restricted cash unit, and cash bonus programs, and Solidigm offers medical, dental, vision, supplemental life and AD&D insurance, short- and long-term disability, healthcare and dependent care flexible spending accounts, and a company match on eligible 401(k) contributions.

Requirements

Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Typically 3 or more years of relevant experience in RTL design and ASIC development.
Strong proficiency in Verilog/SystemVerilog and experience designing complex, synthesizable RTL.
Deep understanding of digital logic, sequential design, finite-state machines, pipelining, timing closure, and computer architecture.
Experience with ASIC design flows, including RTL simulation, lint, synthesis, static timing analysis, and design integration.
Experience analyzing timing reports and optimizing RTL to meet performance, power, and area requirements.
Strong understanding of clocking, reset architecture, CDC, and robust hardware design practices.
Proficiency in scripting or programming with Python, Tcl, Perl, or C/C++ to automate design tasks and analyze results.
Demonstrated ability to debug complex hardware issues, perform root-cause analysis, and collaborate across engineering teams.

Nice To Haves

Experience designing NAND Flash memory controllers, SSD controllers, or other high-performance storage ASICs.
Strong understanding of SSD architecture, Flash Translation Layer interactions, NAND parallelism, and storage data paths.
Experience with NAND interfaces and protocols, including ONFI or Toggle-mode interfaces, and their timing and command requirements.
Knowledge of NAND Flash reliability characteristics, error management, ECC/LDPC, bad-block handling, and read-retry mechanisms.
Experience designing high-throughput data paths, DMA engines, queue management, arbitration, buffering, and memory interfaces.
Familiarity with industry-standard EDA tools for simulation, synthesis, lint, CDC/RDC, and static timing analysis.
Experience with low-power design techniques, clock gating, power management, and PPA optimization.
Experience with formal verification, hardware emulation, FPGA prototyping, or post-silicon debug.
Understanding of interface protocols such as AXI, AHB, PCIe, or NVMe-related controller interfaces.
Experience with design automation, RTL quality analysis, or AI-assisted hardware design and verification workflows.
A track record of technical ownership, cross-functional problem-solving, and delivery of complex ASIC designs from specification through silicon validation.

Responsibilities

Architect, design, and implement complex RTL modules using Verilog/SystemVerilog for NAND Flash memory-based SSD controllers.
Translate system and microarchitecture specifications into efficient, synthesizable, reusable, and maintainable RTL.
Make microarchitecture tradeoffs involving throughput, latency, buffering, concurrency, resource utilization, and scalability.
Design and optimize controller pipelines, state machines, arbitration logic, queues, FIFOs, DMA engines, and memory interfaces.
Develop and optimize logic for NAND command sequencing, interface control, data transfer, status handling, error recovery, and timing management.
Design controller logic for high channel utilization, parallel NAND operations, efficient resource scheduling, and robust error handling.
Collaborate with firmware and architecture teams on hardware/software partitioning and controller-function optimization.
Analyze and optimize RTL to meet timing, throughput, latency, power, and silicon-area targets; identify critical paths, bottlenecks, resource conflicts, and inefficient logic.
Drive design improvements through architectural changes, logic restructuring, pipelining, resource sharing, and power-aware techniques.
Evaluate synthesis and static timing analysis reports and work with physical design teams to resolve timing and implementation challenges.
Own RTL development through synthesis readiness, subsystem integration, and ASIC implementation handoff.
Ensure design quality through applicable lint, clock-domain crossing, reset-domain crossing, and design-rule checks.
Address clocking, reset, initialization, parameterization, and low-power requirements.
Collaborate with verification teams to define verification strategies, resolve functional issues, and achieve robust design coverage.
Support pre-silicon emulation, silicon bring-up, post-silicon debug, and hardware issue root-cause analysis.
Integrate or develop interfaces to ECC/LDPC engines, data-protection logic, and other reliability-related controller subsystems.
Implement error detection, status reporting, recovery sequencing, and fault-handling mechanisms.
Work with reliability and firmware teams on NAND error behavior, data integrity, and system-level fault scenarios.
Drive design reviews, provide technical guidance, and promote RTL coding and design best practices.
Identify design risks, evaluate alternative implementations, and drive cross-functional issues to closure.
Contribute to design methodologies, automation, technical documentation, and continuous improvements in ASIC development efficiency.