Principal Engineer, SoC Design

kepler•San Jose, CA

1d•$250,000 - $310,000

About The Position

Kepler is seeking a highly experienced SoC Chip Lead to own chip implementation for its products. In this technical leadership role, the Principal Engineer will lead design, verification, and physical design teams from micro-architecture through tapeout and post-silicon validation. The role involves end-to-end implementation ownership, design-to-spec execution, IP evaluation and integration, cross-functional coordination, implementation standards and sign-off infrastructure, and leading and mentoring engineers. The position requires extensive hands-on SoC front-end design and implementation experience, expertise across key SoC subsystems and implementation methods, and the ability to drive complex programs.

Requirements

B.Tech, M.Tech, or MS in EE, ECE, Computer Engineering, or a related field.
15+ years of hands-on SoC front-end design and implementation experience, with multiple successful high-performance tapeouts.
Deep expertise in on-chip interconnect, power management, and IO subsystem design.
Strong working knowledge of physical design, including floorplanning, timing convergence, and power integrity.
Hands-on experience with lint, CDC/RDC, LEC, synthesis, SDC development, and formal verification.
Solid knowledge of DFT/DFX methods, including scan insertion, ATPG, MBIST, and JTAG.
Proficiency with industry-standard EDA tools across the implementation stack.
Strong scripting skills in Python, Perl, Tcl, and Shell.
Excellent leadership and communication skills, with a proven ability to drive complex programs in a fast-paced environment.

Nice To Haves

Experience with 3D innovations.
Background in high-bandwidth memory subsystem design.
Familiarity with AI workloads and their memory demands.
Experience with emulation and prototyping platforms.
Prior startup experience delivering silicon with lean teams and aggressive schedules.

Responsibilities

Own end-to-end chip implementation, including front-end design, verification integration, physical design coordination, DFT/DFX, packaging, and manufacturing interaction.
Drive design-to-spec execution across lint, CDC, LEC, synthesis, SDC constraints, and full design convergence.
Evaluate and integrate IP, weighing trade-offs across performance, power, area, cost, and schedule.
Coordinate with architecture, verification, DFX, physical design, packaging, and manufacturing teams to ensure implementation decisions are physically feasible and on schedule.
Set and enforce implementation best practices, review standards, and sign-off infrastructure.
Lead and mentor design and implementation engineers; drive planning, resourcing, and risk mitigation.