Principal Modem SOC Design Engineer - Terawave
About The Position
Blue Origin is developing TeraWave, a satellite communications network intended to provide symmetrical data speeds of up to 6 Tbps worldwide for enterprise, data center, and government users. The Principal Modem SOC Design Engineer will serve as a technical design leader on the ASIC Engineering SOC Team and lead RTL design for the TeraWave modem system-on-chip (SOC) and its subsystems. This is an individual contributor position with technical leadership scope. The engineer will define microarchitecture from communication system specifications and performance requirements, develop Arm compute subsystem logic, and drive integration across modem PHY, Arm compute, debug, and IO infrastructure. The role serves as a technical interface among system architecture, SOC architecture, software architecture, performance modeling, and FPGA prototyping teams, aligning design decisions from specification through production silicon.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12 or more years of experience in digital ASIC or SOC RTL design.
- Experience defining microarchitecture for modem or communication SOC blocks from system specifications.
- Experience with Arm compute subsystem design, including AXI interconnect and SRAM controllers.
- Experience with LPDDR4, LPDDR5, LPDDR6, or other high-speed memory interface subsystems.
- Experience with high-speed Gigabit Ethernet interface subsystems.
- Experience with SOC-level integration, including bus fabric, clock, and reset architecture.
- Experience with debug subsystem design using Arm CoreSight components.
- Experience with synthesis, timing constraint development, and timing closure support.
Nice To Haves
- Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with RTL design in Verilog or System Verilog for modem datapath or PHY IP blocks.
- Experience with signal processing hardware such as filters, FFTs, equalizers, or forward error correction (FEC).
Responsibilities
- Lead RTL design in Verilog or System Verilog for the modem SOC and its subsystems.
- Define microarchitecture based on satellite communication system specifications and performance requirements.
- Develop Arm compute subsystem logic, including AXI interconnect and SRAM controller integration.
- Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure.
- Drive subsystem and SOC-level integration, including clock, reset, and general-purpose IO (GPIO) subsystems.
- Serve as the technical interface to the system architecture, SOC architecture, and software architecture teams.
- Collaborate with performance modeling and FPGA prototyping teams on design decisions and validation.
Benefits
- Medical, dental, and vision insurance.
- Basic and supplemental life insurance.
- Paid parental leave.
- Short- and long-term disability.
- 401(k) with a company match of up to 5%.
- Education Support Program.
- Stock options for all regular employees working at least 20 hours per week.
- Paid time off of up to four weeks per year based on weekly scheduled hours.
- Up to 14 company-paid holidays.
- Depending on role type and job level, employees may be eligible for benefits and bonuses based on individual contributions, company results, or other factors.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
