Principal SOC Performance Analysis Engineer - Terawave

BLUE ORIGIN•San Diego, CA
•$269,175 - $376,844

About The Position

Blue Origin is developing TeraWave, a satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps worldwide for enterprise, data center, and government users. As a Principal SOC Performance Analysis Engineer on the ASIC Engineering SOC Team, you will own performance analysis for a satellite communication System on Chip (SOC). This senior individual-contributor role has technical leadership scope and no direct reports. You will establish performance analysis methodology from pre-silicon modeling through emulation-based verification and post-silicon validation, with findings informing architectural decisions across hardware, firmware, and software teams. Applications are accepted on an ongoing basis until the requisition is closed. The position requires applicants to meet Blue Origin’s stated U.S. citizenship, permanent residency, refugee, or asylum status requirement. Background checks apply as described in the posting. The listed base pay range for California and Washington applicants is $269,175.00–$376,843.95; ranges at other sites may differ.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • At least 10 years of experience in SOC architecture, performance analysis, or verification.
  • Experience with SOC performance modeling for multi-core processor-based designs.
  • Experience with memory subsystem bandwidth and latency analysis for DDR or LPDDR.
  • Experience using hardware emulation platforms for pre-silicon performance or functional testing.

Nice To Haves

  • Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • Experience with satellite communication or wireless physical layer signal processing and L1 functions.
  • Experience with Arm multi-core subsystems supporting Linux SDK or board support package environments.
  • Experience with LPDDR6 or next-generation memory interface bring-up and performance tuning.
  • Experience analyzing high-speed Ethernet performance and packet processing throughput.
  • Proficiency with C, C++, SystemC, or Python for performance modeling and test automation.
  • Strong written and verbal communication skills for presenting analysis results to technical stakeholders.

Responsibilities

  • Develop pre-silicon performance models for satellite communication PHY IP and Arm core subsystem workloads.
  • Analyze multi-channel LPDDR6 bandwidth, latency, and arbitration across concurrent SOC traffic flows.
  • Define and verify performance requirements for L2 acceleration data paths.
  • Characterize Ethernet throughput and packet processing rates under representative load.
  • Execute performance verification and functional testing on emulation platforms before silicon tape out.
  • Validate post-silicon performance against pre-silicon projections and document correlation results.
  • Partition performance budgets across L1 PHY, L2 software, and firmware domains.
  • Collaborate with architecture, design, and software teams to resolve identified performance bottlenecks.

Benefits

  • Medical insurance
  • Dental insurance
  • Vision insurance
  • Basic and supplemental life insurance
  • Paid parental leave
  • Short- and long-term disability
  • 401(k) with company match of up to 5%
  • Education Support Program
  • Stock options for regular employees working at least 20 hours per week
  • Paid time off of up to four weeks per year based on weekly scheduled hours
  • Up to 14 company-paid holidays
  • Depending on role type and job level, employees may be eligible for benefits and bonuses based on individual contributions or company results.
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