Principal Modem PHY IP Design Verification Engineer - Terawave

Blue Origin•Hutto, TX

23h•$269,175 - $376,844

About The Position

Blue Origin is seeking a Principal Modem PHY IP Design Verification Engineer to lead and execute verification of advanced modem PHY IP for the TeraWave program. TeraWave is a satellite communications network intended to provide symmetrical data speeds of up to 6 Tbps through optically interconnected satellites in low Earth orbit and medium Earth orbit. The role develops verification strategies and scalable environments to ensure high-quality modem PHY IP delivery for next-generation wireless ASIC platforms. The engineer will collaborate with PHY architects, RTL designers, systems engineers, firmware, FPGA, and validation teams to verify functionality, performance, and integration across simulation, emulation, prototyping, and silicon bring-up. The position focuses on modem PHY and DSP systems, including correlation of RTL behavior with floating-point, fixed-point, or bit-accurate reference models. The engineer will also work with internal teams and external design service partners to drive verification closure.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
10+ years of experience in digital design verification, ASIC/SoC verification, or modem/baseband verification.
Strong experience with SystemVerilog and modern verification methodologies such as UVM.
Experience developing verification environments for complex DSP, modem, or communications IP.
Familiarity with one or more modem PHY areas: OFDM and/or single-carrier systems; synchronization; channel estimation and equalization; FEC such as LDPC, Polar, Turbo, or BCH; MIMO/beamforming; or fixed-point and quantized signal processing.
Experience with scripting and automation using Python, Perl, shell, or similar tools.
Strong debugging and problem-solving skills across RTL, testbench, and model-correlation issues.
Ability to work closely with design, architecture, and systems teams in a fast-paced development environment.

Nice To Haves

Master’s degree in Electrical Engineering, Computer Engineering, Signal Processing, Communications, or a related field.
Experience verifying modem PHY or baseband IP for mmWave, sub-THz, or Terahertz systems; satellite or space communications; 5G/6G systems; or high-throughput wireless backhaul or mesh systems.
Experience with MATLAB, C/C++, or Python-based reference models for algorithm correlation.
Familiarity with assertions, formal verification, lint, CDC, RDC, and low-power verification methodologies.
Experience with emulation, FPGA prototyping, and post-silicon validation/debug.
Knowledge of RF/system impairments and their impact on modem PHY behavior, including phase noise, frequency offset, nonlinearities, and channel effects.
Experience working with external IP vendors or design service partners.
Ability to operate effectively in an ambiguous, fast-moving development environment.

Responsibilities

Develop and execute verification strategies and plans for modem PHY IP and subsystem-level integration.
Build and maintain block-level and subsystem-level PHY IP verification environments using industry-standard methodologies.
Create testbenches, stimulus, checkers, scoreboards, assertions, and coverage models to verify modem PHY functionality and corner cases.
Verify modulation and demodulation, timing and frequency synchronization, channel estimation and equalization, MIMO and beamforming support, FEC integration, control/configuration/status interfaces, and impairment handling and recovery behavior.
Collaborate with PHY algorithm and architecture teams to correlate RTL behavior against floating-point, fixed-point, or bit-accurate reference models.
Define and track functional, code, assertion, and scenario coverage to assess verification completeness.
Develop constrained-random and directed test strategies for feature, stress, and corner-case validation.
Identify, debug, and root-cause design and integration issues with RTL and architecture teams.
Verify performance-sensitive designs, with attention to throughput, latency, buffering, and protocol timing behavior.
Contribute to regression automation, CI flows, and verification infrastructure improvements.
Support subsystem integration, FPGA prototyping, emulation, and post-silicon debug as needed.
Document verification plans, test results, coverage status, and quality metrics.
Work with internal engineering teams and external design service partners to drive verification closure.

Benefits

Medical insurance
Dental insurance
Vision insurance
Basic and supplemental life insurance
Paid parental leave
Short- and long-term disability
401(k) with company match of up to 5%
Education Support Program
Stock options for regular employees working at least 20 hours per week
Paid time off of up to four weeks per year based on weekly scheduled hours
Up to 14 company-paid holidays
Depending on role type and job level, possible benefits and bonuses based on individual contributions and company results; eligibility and amounts are not guaranteed.